Ml550 System Monitor And Power Monitor Support - Xilinx Virtex-5 FPGA ML550 User Manual

Chapter 3: Hardware Description

ML550 System Monitor and Power Monitor Support

Table 3-13: ML550 System Monitor Connections
System Monitor
Input Channel
VAUXN[9]
VAUXP[9]
VAUXN[10]
VAUXP[10]
VAUXN[11]
VAUXP[11]
VAUXN[12]
VAUXP[12]
VAUXN[13]
VAUXP[13]
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The Virtex-5 FPGA System Monitor block diagram is shown in
VAUXP[0]
VAUXN[0]
Mux
VAUXP[14]
VAUXN[14]
VAUXP[15]
VAUXN[15]
VP
VN
Temperature
°C
Sensor
V
CCINT
V
CCAUX
V
REFP
V
REFN
Supply Sensor
Internal Supplies
Figure 3-11: Virtex-5 FPGA System Monitor
The ML550 board hosts several measurement circuits, external to the FPGA, which are
connected to the upper half of the input channels shown in the block diagram, namely the
inputs VAUXP/N[9:15] and VP/VN). VAUXP/N[0:8] are not supported on the ML550 as
these dual-purpose FPGA pins are used for other functions.
Detailed information concerning the System Monitor block is contained in UG192,
available at the following link:
http://www.xilinx.com/support/documentation/user_guides/ug192.pdf
The ML550 system monitor support circuitry is connected to the XC5VLX50T FFG-1136 as
shown in Table 3-13.
FPGA
Parameter Measured
Pin#
U31 5V Power (N)
U32 5V Power (P)
T34 2.5V V (N)
CCAUX
U33 2.5V V (P)
CCAUX
R32 2.5V V (N)
CCO
R33 2.5V V (P)
CCO
R34 2.5V System (N)
T33 2.5V System (P)
N32 1.0V V (N)
CCINT
P32 1.0V V (P)
CCINT
System Monitor
10-Bits
Mux
200 kSPS
ADC
Signal Name
VCC5V_MON_SM9N
VCC5V_MON_SM9P
VCCAUX2V5_MON_SM10N
VCCAUX2V5_MON_SM10P
VCCO2V5_MON_SM11N
VCCO2V5_MON_SM11P
VCC2V5_MON_SM12N
VCC2V5_MON_SM12P
VCC1V0_MON_SM13N
VCC1V0_MON_SM13P
www.xilinx.com
Figure 3-11.
Register File Interface
00h 40h
01h 41h
02h 42h
03h 43h
Status Registers Control Registers
7Eh
3Eh
7Fh
3Fh
Dynamic
Control Logic Reconfiguration
Port (DRP)
STATUS ALARM DRP
CLOCK
and
JTAG TAP
CONTROL
Controller
FPGA Interconnect
UG202_3_11_041708
Sensor Schematic
Circuit Sheet(s)
R network
R network
R network
R network
R network
R network
R network
R network
R network
R network
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
R
19, 34
19, 34
20, 34
20, 34
20, 34
20, 34
20, 34
20, 34
20, 34
20, 34