Clb/Slice Configurations - Xilinx Virtex-5 FPGA User Manual

CLB/Slice Configurations

Table 5-1
implemented in one of the configurations listed.
all CLBs.
Table 5-1: Logic Resources in One CLB
Notes:
1. SLICEM only, SLICEL does not have distributed RAM or shift registers.
Table 5-2: Virtex-5 FPGA Logic Resources Available in All CLBs
CLB Array
Device
Row x Column
XC5VLX20T 60 x 26
XC5VLX30 80 x 30
XC5VFX30T 80 x 38
XC5VLX30T 80 x 30
XC5VSX35T 80 x 34
XC5VLX50 120 x 30
XC5VLX50T 120 x 30
XC5VSX50T 120 x 34
XC5VFX70T 160 x 38
XC5VLX85 120 x 54
XC5VLX85T 120 x 54
XC5VSX95T 160 x 46
XC5VFX100T 160 x 56
XC5VLX110 160 x 54
XC5VLX110T 160 x 54
XC5VFX130T 200 x 56
XC5VTX150T 200 x 58
XC5VLX155 160 x 76
XC5VLX155T 160 x 76
XC5VFX200T 240 x 68
XC5VLX220 160 x 108
XC5VLX220T 160 x 108
XC5VSX240T 240 x 78
XC5VTX240T 240 x 78
XC5VLX330 240 x 108
XC5VLX330T 240 x 108
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
summarizes the logic resources in one CLB. Each CLB or slice can be
Slices LUTs Flip-Flops
2 8 8
Number of
6-Input LUTs
12,480
19,200
20,480
19,200
21,760
28,800
28,800
32,640
44,800
51,840
51,840
58,880
64,000
69,120
69,120
81,920
92,800
97,280
97,280
122,880
138,240
138,240
149,760
149,760
207,360
207,360
www.xilinx.com
Table 5-2
Arithmetic and
Distributed RAM
Carry Chains
2 256 bits
Maximum
Distributed RAM (Kb)
210
320
380
320
520
480
480
780
820
840
840
1,520
1,240
1,120
1,120
1,580
1,500
1,640
1,640
2,280
2,280
2,280
4,200
2,400
3,420
3,420
CLB Overview
shows the available resources in
(1)
Shift Registers
128 bits
Shift Number of
Register (Kb) Flip-Flops
105 12,480
160 19,200
190 20,480
160 19,200
260 21,760
240 28,800
240 28,800
390 32,640
410 44,800
420 51,840
420 51,840
760 58,880
620 64,000
560 69,120
560 69,120
790 81,920
750 92,800
820 97,280
820 97,280
1140 122,880
1140 138,240
1140 138,240
2100 149,760
1200 149,760
1710 207,360
1710 207,360
(1)
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