Dcm Primitives; Dcm_Base Primitive - Xilinx Virtex-5 FPGA User Manual

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Chapter 2: Clock Management Technology

DCM Primitives

The DCM primitives DCM_BASE and DCM_ADV are shown in
X-Ref Target - Figure 2-2

DCM_BASE Primitive

The DCM_BASE primitive accesses the basic frequently used DCM features and simplifies
the user-interface ports. The clock deskew, frequency synthesis, and fixed-phase shifting
features are available to use with DCM_BASE.
DCM_BASE primitive.
Table 2-2: DCM_BASE Primitive
50
DCM_BASE
CLKIN
CLKFB
RST
CLK2X180
CLKFX180
Available Ports
Clock Input
Control and Data Input
Clock Output
Status and Data Output
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CLK0
CLKIN
CLK90
CLKFB
CLK180
RST
CLK270
PSINCDEC
CLK2X
PSEN
PSCLK
CLKDV
DADDR[6:0]
CLKFX
DI[15:0]
DWE
DEN
LOCKED
DCLK
Figure 2-2: DCM Primitives
Table 2-2
Port Names
CLKIN, CLKFB
RST
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED
Figure
2-2.
DCM_ADV
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
PSDONE
DO[15:0]
DRDY
ug190_2_02_042706
lists the available ports in the
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009

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