Configuration Modes - Xilinx Virtex-5 FPGA ML561 User Manual

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Configuration
This chapter provides a brief description of the FPGA configuration methods used on the
Virtex-5 FPGA ML561 Development Board. This chapter contains the following sections:

Configuration Modes

The Virtex-5 FPGA ML561 Memory Interfaces Development Board includes several
options to configure the Virtex-5 FPGAs. The configuration modes are:
Table 6-1
SelectMAP configuration modes are not supported on the Virtex-5 FPGA ML561
Development Board. A separate 6-pin 3x2 header is provide for each FPGA to control the
Mode bits setting. The three headers are P27, P46, and P112 for FPGA #1, FPGA #2, and
FPGA #3, respectively. The even pins (# 2, 4, and 6) of the headers are tied to GND, and the
odd pins (# 1, 3, and 5) are connected to the respective Mode bit FPGA inputs (M0, M1, and
M2, respectively). A weak (4.7K ) pull-up is applied to each of these pins to set a logic '1'
by default.
Table 6-1: Configuration Modes
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
"Configuration Modes"
"JTAG Chain"
"JTAG Port"
"Parallel IV Cable Port"
"System ACE Interface"
System ACE mode
JTAG mode
shows the Virtex-5 FPGA configuration modes. The Master and Slave (Parallel)
Mode
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
JTAG
www.xilinx.com
XCONFIG JTAG
P72 P114
(1) (2)
X —
X —
— —
— —
— X
Chapter 6
(3,4)
Mode Jumpers
5 -> 6 3 -> 4 1 -> 2
(M2) (M1) (M0)
0 0 0
1 1 1
0 1 1
1 1 0
1 0 1
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