Vhdl And Verilog Templates, And The Clocking Wizard - Xilinx Virtex-5 FPGA User Manual

Hide thumbs Also See for Virtex-5 FPGA:

Table of Contents

X-Ref Target - Figure 2-16

VHDL and Verilog Templates, and the Clocking Wizard

VHDL and Verilog instantiation templates are available in the Libraries Guide for all

primitives. In addition, VHDL and Verilog files are generated by the Clocking Wizard in

the ISE software. The Clocking Wizard sets appropriate DCM attributes, input/output

clocks, and buffers for general use cases.

Virtex-5 FPGA User Guide

UG190 (v5.0) June 19, 2009

VHDL and Verilog Templates, and the Clocking Wizard

Figure 2-16: Two DCMs Driving a PLL

www.xilinx.com

ug190_2_18_040906