Block Ram And Fifo Ecc Port Descriptions - Xilinx Virtex-5 FPGA User Manual

Chapter 4: Block RAM

Block RAM and FIFO ECC Port Descriptions

Table 4-21
Table 4-21: Block RAM ECC Port Names and Descriptions
Port Name Direction
DI[63:0] Input
DIP[7:0] Input
WRADDR[8:0] Input
RDADDR[8:0] Input
WREN Input
RDEN Input
SSR Input
WRCLK Input
RDCLK Input
DO[63:0] Output
DOP[7:0] Output
(1)
SBITERR Output
(1)
DBITERR Output
ECCPARITY[7:0] Output
Notes:
1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error
detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and
DBITERR indicate these three conditions.
162
lists and describes the block RAM ECC I/O port names.
Data input bus.
Data input parity bus. Used in decode-only mode to input the precalculated ECC
parity bits.
Write address bus.
Read address bus.
Write enable. When WREN = 1, data will be written into memory. When WREN = 0,
write is disabled
Read enable. When RDEN = 1, data will be read from memory. When RDEN = 0, read
is disabled.
Not supported when using the block RAM ECC primitive. Always connect to GND.
Clock for write operations.
Clock for read operations.
Data output bus.
Data output parity bus. Used in encode-only mode to output the stored ECC parity
bits.
Single-bit error status.
Double-bit error status.
ECC encoder output bus.
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Signal Description
UG190 (v5.0) June 19, 2009
Virtex-5 FPGA User Guide