Lvdci (Low Voltage Digitally Controlled Impedance) - Xilinx Virtex-5 FPGA User Manual

Table 6-8
standard.
Table 6-8: Allowed Attributes for the LVCMOS12 I/O Standard

LVDCI (Low Voltage Digitally Controlled Impedance)

Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as LVTTL,
LVCMOS, etc., must have a drive impedance that matches the characteristic impedance of
the driven line. Virtex-5 devices provide a controlled impedance output driver to provide
series termination without external source termination resistors. The impedance is set by
the common external reference resistors, with resistance equal to the trace characteristic
impedance, Z
Sample circuits illustrating both unidirectional and bidirectional termination techniques
for a controlled impedance driver are shown in
standards supporting a controlled impedance driver are: LVDCI_15, LVDCI_18,
LVDCI_25, and LVDCI_33.
X-Ref Target - Figure 6-31
X-Ref Target - Figure 6-32
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
details the allowed attributes that can be applied to the LVCMOS12 I/O
Attributes
IOSTANDARD
DRIVE
SLEW
.
0
LVDCI
R 0 = R VRN = R VRP = Z 0
Figure 6-31: Controlled Impedance Driver with Unidirectional Termination
LVDCI
R 0 = R VRN = R VRP = Z 0
Figure 6-32: Controlled Impedance Driver with Bidirectional Termination
www.xilinx.com
Specific Guidelines for I/O Supported Standards
Primitives
IBUF/IBUFG OBUF/OBUFT
LVCMOS12 LVCMOS12
UNUSED
UNUSED {FAST, SLOW}
Figure 6-31
IOB
Z 0
IOB
Z 0
IOBUF
LVCMOS12
2, 4, 6, 8 2, 4, 6, 8
{FAST, SLOW}
and Figure 6-32. The DCI I/O
IOB
LVDCI
ug190_6_28_022806
IOB
LVDCI
R 0 = R VRN = R VRP = Z 0
ug190_6_29_022806
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