Jitter Filter; Limitations; Vco Operating Range; Minimum And Maximum Input Frequency - Xilinx Virtex-5 FPGA User Manual

Chapter 3: Phase-Locked Loops (PLLs)
PLL outputs are programmed to provide a 533 MHz PowerPC® processor clock, a
266 MHz PowerPC processor gasket clock, a 178 MHz clock, a 133 MHz memory interface
clock, a 66 MHz PCI™ clock, and a 33 MHz PCI clock. In this example, there are no
required phase relationships between the reference clock and the output clocks, but there
are required relationships between the output clocks.
X-Ref Target - Figure 3-5

Jitter Filter

PLLs always reduce the jitter inherent on a reference clock. The PLL can be instantiated as
a standalone function to simply support filtering jitter from an external clock before it is
driven into the another block (including the DCM). As a jitter filter, it is usually assumed
that the PLL acts as a buffer and regenerates the input frequency on the output (e.g.,
F
PLL attribute BANDWIDTH set to Low. Setting the BANDWIDTH to Low can incur an
increase in the static offset of the PLL.

Limitations

The PLL has some restrictions that must be adhered to. These are summarized in the PLL
electrical specification in the Virtex-5 FPGA Data Sheet. In general, the major limitations are
VCO operation range, input frequency, duty cycle programmability, and phase shift.

VCO Operating Range

The minimum and maximum VCO operating frequencies are defined in the electrical
specification of the Virtex-5 FPGA Data Sheet. These values can also be extracted from the
speed specification.

Minimum and Maximum Input Frequency

The minimum and maximum CLKIN input frequency are defined in the electrical
specification of the Virtex-5 FPGA Data Sheet.

Duty Cycle Programmability

Only discrete duty cycles are possible given a VCO operating frequency. The counter
settings to determine the output duty cycle is further discussed under
94
33 MHz
Reference
Clock
Figure 3-5: PLL as a Frequency Synthesizer
= 100 MHz, F = 100 MHz). In general, greater jitter filtering is possible by using the
IN OUT
www.xilinx.com
PFD, CP,
D = 1 D0 = 1
LF, VCO
D0 = 2
M = 16
D0 = 3
D0 = 4
D0 = 8
D = 16
PowerPC Processor Core
PowerPC Processor Gasket
CLB/Fabric
Memory Interface
PCI-66
PCI-33
UG190_3_05_111808
"Counter Control."
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009