Memory Interface Type; Iserdes Width Expansion - Xilinx Virtex-5 FPGA User Manual

Memory Interface Type

The only valid clocking arrangements for the ISERDES_NODELAY block using the
memory interface type are:
•
•
•
The clocking arrangement using BUFIO and BUFR is shown in
CLKDIV inputs must be nominally phase-aligned. For example, if CLK and CLKDIV in
Figure 8-6
clocking arrangement is a legal BUFIO/BUFR configuration, the clocks would still be out
of phase. No phase relationship between CLK and OCLK is expected. Calibration must be
performed for reliable data transfer from CLK to OCLK domain.
Strobe-Based Memory Interfaces - OCLK"
data between CLK and OCLK.
X-Ref Target - Figure 8-6

ISERDES Width Expansion

Two ISERDES modules are used to build a serial-to-parallel converter larger than 1:6. In
every I/O tile there are two ISERDES modules; one master and one slave. By connecting
the SHIFTOUT ports of the master ISERDES to the SHIFTIN ports of the slave ISERDES the
serial-to-parallel converter can be expanded to up to 1:10 (DDR) and 1:8 (SDR).
Figure 8-7
master and slave ISERDES modules. Ports Q3 - Q6 are used for the last four bits of the
parallel interface on the slave ISERDES.
For a differential input, the master ISERDES must be on the positive side of the differential
input pair. When the input is not differential, the input buffer associated with the slave
ISERDES is not available and can not be used.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
CLK driven by BUFIO or BUFG
OCLK driven by DCM and CLKDIV driven by CLKDV output of same DCM
OCLK driven by PLL and CLKDIV driven by CLKOUT[0:5] of same PLL
were inverted by the designer at the ISERDES inputs, then although the
Clock
Input
Figure 8-6: Clocking Arrangement Using BUFIO and BUFR
illustrates a block diagram of a 1:10 DDR serial-to-parallel converter using the
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Input Serial-to-Parallel Logic Resources (ISERDES)
gives further information about transferring
ISERDES_NODELAY
BUFIO
BUFR ( ÷ X)
Figure 8-6. The CLK and
"High-Speed Clock for
CLK
CLKDIV
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