Gtlp (Gunning Transceiver Logic Plus); Gtlp_Dci Usage - Xilinx Virtex-5 FPGA User Manual

Table 6-13: GTL DC Voltage Specifications (Continued)
Notes:
1. N must be greater than or equal to 0.653 and less than or equal to 0.68.

GTLP (Gunning Transceiver Logic Plus)

The Gunning Transceiver Logic Plus, or GTL+ standard is a high-speed bus standard
(JESD8.3) first used by the Pentium Pro Processor. This standard requires a differential
amplifier input buffer and a open-drain output buffer. The negative terminal of the
differential input buffer is referenced to the V
A sample circuit illustrating a valid termination technique for GTL+ with external parallel
termination and unconnected V
X-Ref Target - Figure 6-38
V

GTLP_DCI Usage

GTL+ does not require a V
to 1.5V. GTLP_DCI provides single termination to V
A sample circuit illustrating a valid termination technique for GTLP_DCI with internal
parallel driver and receiver termination is shown in
X-Ref Target - Figure 6-39
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Parameter
V
OL
I at V (mA)
OH OH
I at V (mA) at 0.4V
OL OL
I at V (mA) at 0.2V
OL OL
IOB
R = Z 0 = 50Ω
P
= Unconnected
CCO
Figure 6-38: GTL+ with External Parallel Termination and Unconnected V
= 1.5V
V
CCO
50Ω
Figure 6-39: GTLP_DCI Internal Parallel Driver and Receiver Termination
www.xilinx.com
Specific Guidelines for I/O Supported Standards
Min
–
–
32
-
pin.
REF
is shown in Figure
CCO
V = 1.5V V = 1.5V
TT TT
R
P
Z 0 = 50
voltage. However, for GTLP_DCI, V
CCO
IOB
Z 0 = 50
Typ Max
0.2 0.4
– –
– –
– 40
6-38.
IOB
= Z 0 = 50Ω
V = 1.0V
REF
must be connected
CCO
for inputs or outputs.
CCO
Figure 6-39.
IOB
= 1.5V
V
CCO
R VRP = Z 0 = 50Ω
+
–
V = 1.0V
REF
ug190_6_37_030206
+
–
ug190_6_36_030206
CCO
249