Pll In Virtex-4 Fpga Pmcd Legacy Mode - Xilinx Virtex-5 FPGA User Manual

PLL in Virtex-4 FPGA PMCD Legacy Mode

Virtex-5 devices do not have Phase-Matched Clock Dividers (PMCDs). The Virtex-5 FPGA
PLL supports the Virtex-4 FPGA PMCD mode of operation. To take advantage of the
inherently more powerful features of the Virtex-5 FPGA PLL, Xilinx recommends
redesigning Virtex-4 FPGA PMCDs by implementing PLLs directly. The difference
between the Virtex-5 FPGA PLL and the Virtex-4 FPGA PMCD block in Virtex-4 FPGA
PMCD legacy mode is that only two clock inputs are supported in the Virtex-5 device
implementation. The Virtex-4 device implementation supported up to four clock inputs. If
four clock inputs must be used, then two PLLs can be put into PMCD mode. In this case,
delay matching is not optimal.
Figure 3-17
can not be used as a PLL if it is already being used as a PMCD. To design-in the Virtex-5
FPGA PMCD functionality, instantiate a Virtex-4 FPGA PMCD primitive. ISE software
maps the Virtex-4 FPGA PMCD primitive into a Virtex-5 FPGA PLL.
X-Ref Target - Figure 3-17
Table 3-8
the Virtex-4 FPGA PMCD port names.
Table 3-8: Mapping of Port Names
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
shows the Virtex-4 FPGA PMCD primitive implemented using a PLL. A PLL
CLKFBIN
CLKIN
Figure 3-17: PMCD Primitive Implemented Using the PLL in PMCD Legacy Mode
shows the port mapping between Virtex-5 FPGA PLL in PMCD legacy mode and
Virtex-4 FPGA
Port Name
CLKA
CLKB
CLKC
CLKD
CLKA1
CLKA1D2
CLKA1D4
CLKA1D8
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PLL in Virtex-4 FPGA PMCD Legacy Mode
CLKFBOUT
O0
O1
O2
O3
Virtex-5 FPGA
Port Name
CLKIN
CLKFBIN
n/a
n/a
CLKOUT3
CLKOUT2
CLKOUT1
CLKOUT0
To BUFG
ug190_3_16_022207
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