Bufr Use Models - Xilinx Virtex-5 FPGA User Manual

BUFR Use Models

BUFRs are ideal for source-synchronous applications requiring clock domain crossing or
serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic
resources in the FPGAs other than the IOBs.
X-Ref Target - Figure 1-22
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
Clock Capable I/O
I/O Tile
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
BUFIO
BUFR
Figure 1-22: BUFR Driving Various Logic Resources
www.xilinx.com
Regional Clocking Resources
Figure 1-22 is a BUFR design example.
To Region
Above
CLBs
CLBs
Block
RAM
CLBs
CLBs
CLBs
CLBs
Block
RAM
CLBs
CLBs
To Region
Below
DSP
Tile
DSP
Tile
To Center
of Die
UG190_c1_22_022609
45