Chapter 2: Clock Management Technology; Clock Management Summary - Xilinx Virtex-5 FPGA User Manual

Clock Management Technology

Clock Management Summary

The Clock Management Tiles (CMTs) in the Virtex-5 family provide very flexible, high-
performance clocking. Each CMT contains two DCMs and one PLL.
simplified view of the center column resources including the CMT block, where the DCM
is located. Each CMT block contains two DCMs and one PLL.
X-Ref Target - Figure 2-1
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
I/O Banks
(Larger Devices Only)
CMT Blocks
(Top Half DCMs/PLLs)
Clock I/O
(Top Half)
Config I/O
(Top Half)
Config Blocks and
BUFGs
Config I/O
(Bottom Half)
Clock I/O
(Bottom Half)
CMT Blocks
(Bottom Half DCMs/PLLs)
I/O Banks
(Larger Devices Only)
Figure 2-1: CMT Location
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Chapter 2
Figure 2-1 shows a
Virtex-5 FPGA
Center Column
UG190_c2_01_022609
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