General Usage Description; Pll Primitives; Pll_Base Primitive - Xilinx Virtex-5 FPGA User Manual

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Table of Contents

Chapter 3: Phase-Locked Loops (PLLs)

General Usage Description

X-Ref Target - Figure 3-4

The PLL_BASE primitive provides access to the most frequently used features of a stand

alone PLL. Clock deskew, frequency synthesis, coarse phase shifting, and duty cycle

programming are available to use with the PLL_BASE. The ports are listed in

Table 3-1: PLL_BASE Ports

shows the two Virtex-5 FPGA PLL primitives, PLL_BASE and PLL_ADV.

Control Inputs

Clock Output

Status and Data Outputs

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Figure 3-4: PLL Primitives

CLKIN, CLKFBIN

CLKOUT0 to CLKOUT5, CLKFBOUT

UG190_c3_04_022709

Virtex-5 FPGA User Guide

UG190 (v5.0) June 19, 2009