Vref System Monitor - Xilinx Virtex-5 FPGA ML550 User Manual

Chapter 3: Hardware Description
2.5V V
The signal conditioning network is shown in
VCC2V5_VAUX
L2
HZ0805E601R-00
1 2
SM_AVDD
30,U9.T18
30,J19.8
REF_2V5_OUT
19,U11.4
30,J19.7
SM_VREF_P
30,U9.V18
Figure 3-19: System Monitor 2.5V Reference Selection using P39 (Sheet 19)
P39 is a 3-pin male right-angle header with pins on 0.1-inch centers. The right-angle pins
face Samtec connector P73. Depending on the length of the P39 pins, it could be difficult to
install/remove the 2-pin jumper block used to select the SM_AVDD voltage on the P39.2
center pin.
To alleviate any mechanical interference between the 2-pin jumper block and the body of
P73, P39 pins can be clipped shorter or bent slightly upwards to permit the 2-pin jumper
block to pass above the body of P73.
P39 must be a right-angle header to keep its profile beneath the LVDS Loopback board
whenever it is installed across the Samtec LVDS connectors.
System Monitor users should install the 2-pin shunt across P39 pins 1 - 2 to select the
precision 2.5V U10 REF3025 output (see
Table 3-14: System Monitor 2.5V AVDD Reference Options
40
System Monitor
REF
HDR_1X3_RA
P39
3 2 1
1
C91
1µF
2
L1
HZ0805E601R-00
1 2
1
C94
0.1µF
2
P39 Pins
1 - 2 U10 TI REF3025 precision 2.5V reference
2 - 3 Filtered 2.5V V
www.xilinx.com
Figure 3-19.
VCC5
L4
HZ0805E601R-00
1
2
1
C92
0.1µF
2
A
2
OUT
3
AGND
1
IN
U10
TI_REF3025_LF
SOT23-3
A
Table 3-14).
Selected Reference Voltage
FPGA power plane
AUX
ML550 Networking Interfaces Platform
VCC5_SYSMON_TAP
MAX6043 not
available in LF/RoHS
1
C99
1µF
2
UG202_3_19_041508
UG202 (v1.4) April 18, 2008
R
19,R282.2
19,C305.1