Pll_Adv Primitive; Clock Network Deskew; Frequency Synthesis Only - Xilinx Virtex-5 FPGA User Manual

PLL_ADV Primitive

The PLL_ADV primitive provides access to all PLL_BASE features plus additional ports
for clock switching, connectivity to DCMs in the same CMT, and access to the Dynamic
Reconfiguration Port (DRP). The ports are listed in
can be found in the Virtex-5 FPGA Configuration Guide.
Table 3-2: PLL_ADV Ports
Notes:
1. REL is used in PMCD mode only. In PLL mode, leave REL unconnected or tied Low.
The Virtex-5 FPGA PLL is a mixed signal block designed to support clock network deskew,
frequency synthesis, and jitter reduction. These three modes of operation are discussed in
more detail within this section. The Voltage Controlled Oscillator (VCO) operating
frequency can be determined by using the following relationship:
where the M, D, and O counters are shown in
The six "O" counters can be independently programmed. For example, O0 can be
programmed to do a divide-by-two while O1 is programmed for a divide by three. The
only constraint is that the VCO operating frequency must be the same for all the output
counters since a single VCO drives all the counters.

Clock Network Deskew

In many cases, designers do not want to incur the delay on a clock network in their I/O
timing budget therefore they use a PLL or DLL to compensate for the clock network delay.
Virtex-5 FPGA PLLs support this feature. A clock output matching the reference clock
CLKIN frequency (usually CLKFBOUT) is connected to a BUFG and fed back to the
CLKFBIN feedback pin of the PLL. The remaining outputs can still be used to divide the
clock down for additionally synthesized frequencies. In this case, all output clocks have a
defined phase relationship to the input reference clock.

Frequency Synthesis Only

The PLLs can also be used for stand alone frequency synthesis. In this application, the PLL
can not be used to deskew a clock network, but rather generate an output clock frequency
for other blocks. In this mode, the PLL feedback path should be set to INTERNAL since it
keeps all the routing local and should minimize the jitter.
configured as a frequency synthesizer. In this example, an external 33 MHz reference clock
is available. The reference clock can be a crystal oscillator or the output of another PLL.
Setting the M counter to 16 makes the VCO oscillate at 533 MHz (33.333 MHz x 16). The six
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Description
Clock Input
Control and Data Input
Clock Output
Status and Data Output
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Table
CLKIN1, CLKIN2, CLKFBIN, DCLK
RST, CLKINSEL, DWE, DEN, DADDR, DI, REL
CLKOUT0 to CLKOUT5, CLKFBOUT,
CLKOUTDCM0 to CLKOUTDCM5, CLKFBDCM
LOCKED, DO, DRDY
M
×
---- -
F = F
VCO CLKIN
D
M
×
-------- -
F F
=
OUT CLKIN
DO
Figure
General Usage Description
3-2. Detailed DRP information
Port
(1)
Equation 3-1
Equation 3-2
3-3.
Figure 3-5 shows the PLL
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