Case 2: Writing To A Full Or Almost Full Fifo - Xilinx Virtex-5 FPGA User Manual

Chapter 4: Block RAM
Clock Event 2 and Clock Event 4: Write Operation and Deassertion of Almost
EMPTY Signal
Three read-clock cycles after the fourth data is written into the FIFO, the Almost EMPTY
pin is deasserted to signify that the FIFO is not in the almost EMPTY state.
For the example in
event 2 is with respect to write-clock, while clock event 4 is with respect to read-clock.
Clock event 4 appears three read-clock cycles after clock event 2.
•
•
•
•
If the rising WRCLK edge is close to the rising RDCLK edge, AEMPTY could be deasserted
one RDCLK period later.

Case 2: Writing to a Full or Almost Full FIFO

Prior to the operations performed in
example, the timing diagram reflects of both standard and FWFT modes.
X-Ref Target - Figure 4-22
WRERR
152
Figure
At time T , before clock event 2 (WRCLK), data 03 becomes valid at the DI
FDCK_DI
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At clock event 4, DO output pins of the FIFO remains at 00 since no read has been
performed. In the case of standard mode, data 00 will never appear at the DO output
pins of the FIFO.
At time T
FCKO_AEMPTY
the AEMPTY pin. In the case of standard mode, AEMPTY deasserts in the same way
as in FWFT mode.
1
WRCLK
WREN
DI
00
RDCLK
RDEN
FULL
AFULL
Figure 4-22: Writing to a Full / Almost Full FIFO
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4-21, the timing diagram is drawn to reflect FWFT mode. Clock
, after clock event 4 (RDCLK), almost empty is deasserted at
Figure 4-22, the FIFO is almost completely full. In this
T
FCCK_WREN
T T
FDCK_DI FDCK_DI
01 02
T
FCKO_FULL
T
FCKO_AFULL
2 3
T
FCCK_WREN
03 04 05
T
FCKO_WERR
T
FCKO_WERR
ug190_4_18_012605
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
4
T
FDCK_DI
06