Ddr2 Component Write Operation - Xilinx Virtex-5 FPGA ML561 User Manual
Memory interfaces development board
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DDR2 Component Write Operation
This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from FPGA1 (U7)
to the DDR2 memory component (U12) measured at 333 MHz (667 Mb/s), where the unit
interval (UI) = 1.5 ns.
28.5 ohms
3.579 ps
71.0 ohms
U12.D3
0.022 in
27.482 ps
DDR2_DQ_BY2_B3
AutoPadstk_3
TL2
TL3
MT47H32M16CC_...
DQ11
DDR2_D...
22.9 fF
Figure 7-3: Post-Layout IBIS Schematics of DDR2 Component Write Data Bit (DDR2_DQ_BY2_B3)
Table 7-1: Circuit Elements of DDR2 Component Write Data Bit
(DDR2_DQ_BY2_B3)
Table 7-2: DDR2 Component Write Operation Correlation Results
Measurement
Hardware at probe
point
Simulation correlation
slow-weak corner
Correlation Delta:
HW vs. Simulation
Extrapolation at IOB
slow-weak corner
Extrapolation at IOB
fast-strong corner
Notes:
1. DVW = Data Valid Window, ISI = Inter-Symbol Interference
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
49.0 ohms
58.3 ohms
24.721 ps
25.244 ps
0.164 in
AutoPadstk_19
DDR2_DQ_BY2_B3
TL4
TL8
DDR2_D...
DDR2_D...
C9
58.1 fF
22.9 fF
500.0 fF
Element
Driver
U7.P25
Receiver
U12.D3
Probe Point
C9
PCB Termination
None
Trace Length
TL 2, 4, 9, 6, 1
(1)
DVW
ISI
(%UI)
(% UI)
(80 + 80) = 160 ps
1.18 ns
(78.7%)
(10.7%)
(77 + 36) = 113 ps
1.22 ns
(81.3%)
(7.5%)
40 ps
47 ps
(2.6%)
(3.2%)
(91 + 36) = 127 ps
1.27 ns
(84%)
(8.5%)
(34 + 20) = 54 ps
1.39 ns
(92%)
(3.7%)
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Signal Integrity Correlation Results
49.1 ohms
49.1 ohms
47.132 ps
445.560 ps
0.302 in
2.852 in
DDR2_DQ_BY2_B3
DDR2_DQ_BY2_B3
TL9
TL6
DDR2_D...
140.8 fF
Designation
FPGA SSTL18_II_DCI_O
DDR2 Memory, 75
Via under the memory device
ODT75 at load
3.37 inches
Noise Margin
(VIH, + VIL) = Total
(% of VREF)
(274 + 384) = 658 mV
(73.1%)
(294 + 266) = 560 mV
(62.2%)
98 mV
(10.9%)
(300 + 270) = 570 mV
(63.3%)
(406 + 351) = 757 mV
(84.1%)
28.5 ohms
21.2 ohms
4.473 ps
1.000 ps
0.028 in
AutoPadstk_3
DDR2_DQ_BY2_B3
TL5
TL1
Virtex-5 FPGA
DDR2_DQ_BY2_B3
DDR2_D...
C7
DDR2_D...
22.9 fF
365.6 fF
500.0 fF
UG199_c7_03_071907
Description
ODT
Overshoot / Undershoot
Margin
(% of VREF)
(550 + 470) = 1020 mV
(113.3%)
(461 + 490) = 951 mV
(105.7%)
69 mV
(7.6%)
(469 + 501) = 970 mV
(107.8%)
(304 + 381) = 685 mV
(76.1%)
U7.P25
59
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