Status Flags; Empty Flag - Xilinx Virtex-5 FPGA User Manual

X-Ref Target - Figure 4-20

Status Flags

Table 4-16
FIFO. Synchronous FIFOs do not have a clock cycle latency when asserting or deasserting
flags. Due to the asynchronous nature of the clocks, the simulation model only reflects the
deassertion latency cycles listed.
Table 4-16: Multirate FIFO Flag Assertion and Deassertion Latency
Notes:
1. Latency is with respect to RDCLK and WRCLK.
2. Depending on the offset between read and write clock edges, the Empty and Full flags can deassert
3. Depending on the offset between read and write clock edges, the Almost Empty and Almost Full flags

Empty Flag

The Empty flag is synchronous with RDCLK, and is asserted when the last entry in the
FIFO is read. When there are no more valid entries in the FIFO queue, the read pointer will
be frozen. The Empty flag is deasserted after three (in standard mode) or four (in FWFT
mode) read clocks after new data is written into the FIFO.
The empty flag is used in the read clock domain. The rising edge of EMPTY is inherently
synchronous with RDCLK. The empty condition can only be terminated by WRCLK,
usually asynchronous to RDCLK. The falling edge of EMPTY must, therefore, artificially
be moved onto the RDCLK time domain. Since the two clocks have an unknown phase
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
RDCLK
RDEN
EMPTY
DO (Standard)
DO (FWFT)
Figure 4-20: Read Cycle Timing (Standard and FWFT Modes)
shows the number of clock cycles to assert or deassert each flag of a multirate
Status Flag
(2)
EMPTY
(2)
FULL
(3)
ALMOST EMPTY
(3)
ALMOST FULL
READ ERROR
WRITE ERROR
one cycle later.
can deassert one cycle later.
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Previous Data
W1
W1 W2
Write/Read Cycle Latency
Assertion
Standard FWFT
0 0
0 0
1 1
1 1
0 0
0 0
FIFO Operations
W2 W3
W3
ug190_4_17_032506
(1)
Deassertion
Standard FWFT
3 4
3 3
3 3
3 3
0 0
0 0
145