Mixing Techniques - Xilinx Virtex-5 FPGA User Manual

Chapter 6: SelectIO Resources
The connection scheme shown in
performance may be degraded by R
value and performance with an IBIS simulation.
X-Ref Target - Figure 6-93
When designing with the LVDCI_33 standard:
•
•
•
In addition, changing the slew rate from fast to slow and/or reducing the current drive
could significantly reduce overshoot and undershoot.
The Virtex-5 FPGA PCB Designer's Guide contains additional design information to assist
PCB designers and signal integrity engineers.
Regulating V
The following section discusses alternatives for managing overshoot and undershoot for
LVTTL, LVCMOS33, and PCI applications.
When V
limits any overshoot higher than 3.5V before reaching the absolute maximum level of
4.05V. In addition, instead of –0.3V when V
corresponding to V
undershoot before reaching the lower absolute maximum limit.
As a result, lowering V
for all supported 3.3 V standards, including LVCMOS_33, LVTTL, LVDCI_33, and PCI.

Mixing Techniques

Either using LVDCI_33 standard or lowering the V
address overshoot and undershoot. It is also acceptable to combine both methods. When
V
The VRP and VRN values should always be the same as the board trace impedance.
304
OBUFT_LVDCI_33
IBUF_LVDCI
Virtex-5
FPGA
Figure 6-93: 3.3V I/O Configuration
The output drive strength and slew rates are not programmable. The output
impedance references the VRP and VRN resistors, and the output current is
determined by the output impedance.
If only LVDCI_33 inputs are used, it is not necessary to connect VRP and VRN to
external reference resistors. The implementation pad report does not record VRP and
VRN being used. External reference resistors are required only if LVDCI_33 outputs
are present in a bank.
LVDCI_33 is compatible with LVTTL and LVCMOS standards only.
at 3.0V
CCO
is lowered to 3.0V, the power clamp diode turns on at about 3.5V. Therefore it
CCO
= 3.0V is –1.05V. In this case, the ground clamp diode clips
CCO
CCO
is lowered to 3.0V, it is not necessary to adjust the reference resistors VRP and VRN.
CCO
www.xilinx.com
Figure 6-93 is for a bidirectional bus scenario. The signal
. Therefore, it is also recommended to verify the R
0
R
Z
0
= 3.75V, the lower absolute maximum limit
CCO
to 3.0V addresses the overshoot and undershoot specifications
CCO
0
External Device
ug190_6_87_030506
to 3.0V is a good approach to
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
0