Clock-Capable I/O Pins Associated With Clock Inputs - Xilinx Virtex-5 FPGA ML555 User Manual

Chapter 3: Hardware Description
Figure 3-13
operation. The parallel mode has priority over serial mode.
SCLOCK
SDATA
T1
STROBE
M,N
PLOAD

Clock-Capable I/O Pins Associated with Clock Inputs

Some clock-capable input and output pins of the FPGA are connected to clocking sources
on the ML555 board.
along with their FPGA bank numbers and I/O bank reference voltages.
Table 3-26: FPGA Clock-Capable I/O Connectivity
Signal Name
PCIBUSCLK1
FPGA_CLK_30MHZ
GPIO2_I10_N
GP1O2_I10_P
GPIO2_I11_N
GP1O2_I11_P
GPIO2_I12_N
GP1O2_I12_P
GPIO2_I13_N
GP1O2_I13_P
70
is a timing diagram showing the serial and parallel programming modes of
T0 N1 N0 M8
NULL
SCLOCK
20 ns min.
SDATA
STROBE
M,N
PLOAD
Figure 3-13: Serial Configuration Interface Timing
Table 3-26
FPGA Pin FPGA Bank Bank V
L34 11
AD32 13
V7
W7
AF5
AG5
18
AF6
AE7
Y6
W6
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M7 M6
100 ns max.
20 ns min.
summarizes these FPGA clock capable inputs and outputs,
(Volts)
CCO
3.0 Regional PCI bus applications
3.0 User defined
User-defined LVDS general-purpose I/O
2.5
interface
Virtex-5 FPGA ML555 Development Kit
M2 M1 M0
UG201_c3_12_092706
Function
UG201 (v1.4) March 10, 2008
R