Chapter 6: Selectio Resources; I/O Tile Overview - Xilinx Virtex-5 FPGA User Manual

SelectIO Resources

I/O Tile Overview

Input/output characteristics and logic resources are covered in three consecutive chapters.
Chapter 6, "SelectIO Resources"
input receivers, and gives detailed examples of many standard interfaces.
"SelectIO Logic Resources,"
Double-Data-Rate (DDR) operation, and the programmable input delay (IDELAY).
Chapter 8, "Advanced SelectIO Logic Resources,"
serializer/deserializer (SERDES).
An I/O tile contains two IOBs, two ILOGICs, two OLOGICs, and two IODELAYs.
Figure 6-1
X-Ref Target - Figure 6-1
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
describes the electrical behavior of the output drivers and
describes the input and output data registers and their
shows a Virtex-5 FPGA I/O tile.
IODELAY
(Chapter 7)
ILOGIC
(Chapter 7)
or
ISERDES
(Chapter 8)
OLOGIC
(Chapter 7)
or
OSERDES
(Chapter 8)
ILOGIC
(Chapter 7)
or
ISERDES
(Chapter 8)
OLOGIC
(Chapter 7)
or
OSERDES
(Chapter 8)
IODELAY
(Chapter 7)
Figure 6-1: Virtex-5 FPGA I/O Tile
www.xilinx.com
Chapter 6
describes the data
IOB
Pad
(Chapter 6)
IOB
Pad
(Chapter 6)
ug190_6_01_041106
Chapter 7,
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