Timing Characteristics - Xilinx Virtex-5 FPGA User Manual

Timing Characteristics

Figure 5-26
X-Ref Target - Figure 5-26
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Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
illustrates the general timing characteristics of a Virtex-5 FPGA slice.
CLK
CE
AX/BX/CX/DX
(DATA)
SR (RESET)
AQ/BQ/CQ/DQ
(OUT)
Figure 5-26: General Slice Timing Characteristics
At time T before clock event (1), the clock-enable signal becomes valid-High at the
CEO
CE input of the slice register.
At time T before clock event (1), data from either AX, BX, CX, or DX inputs
DICK
become valid-High at the D input of the slice register and is reflected on either the
AQ, BQ, CQ, or DQ pin at time T
At time T before clock event (3), the SR signal (configured as synchronous reset)
SRCK
becomes valid-High, resetting the slice register. This is reflected on the AQ, BQ, CQ,
or DQ pin at time T after clock event (3).
CKO
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1 2 3
T
CEO
T
DICK
T
CKO
after clock event (1).
CKO
CLB / Slice Timing Models
T
SRCK
T
CKO
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