Num_Ce Attribute; Serdes_Mode Attribute; Iserdes_Nodelay Clocking Methods; Networking Interface Type - Xilinx Virtex-5 FPGA User Manual

Chapter 8: Advanced SelectIO Logic Resources
X-Ref Target - Figure 8-5

NUM_CE Attribute

The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used. The
possible values are 1 and 2 (default = 2).

SERDES_MODE Attribute

The SERDES_MODE attribute defines whether the ISERDES_NODELAY module is a
master or slave when using width expansion. The possible values are MASTER and
SLAVE. The default value is MASTER. See

ISERDES_NODELAY Clocking Methods

Networking Interface Type

The phase relationship of CLK and CLKDIV is important in the serial-to-parallel
conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.
There are several clocking arrangements within the FPGA to help the design meet the
phase relationship requirements of CLK and CLKDIV. The only valid clocking
arrangements for the ISERDES_NODELAY block using the networking interface type are:
•
•
•
360
D
FF0
ICE
FF1
ICE
CLK
OCLK
CLKDIV
Figure 8-5: Internal Connections of ISERDES_NODELAY When in Memory Mode
CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM
CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL
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FF2
ICE
FF3
ICE
FF4
FF5
"ISERDES Width Expansion."
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Q1
FF6
Q2
FF7
Q3
FF8
Q4
FF9
ug190_8_05_100307