Bitslip Operation - Bitslip; Clock Enable Inputs - Ce1 And Ce2 - Xilinx Virtex-5 FPGA User Manual

Chapter 8: Advanced SelectIO Logic Resources
X-Ref Target - Figure 8-3

Bitslip Operation - BITSLIP

The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted
(active High). Subsequently, the data seen on the Q1 to Q6 output ports will shift, as in a
barrel-shifter operation, one position every time Bitslip is invoked (DDR operation is
different from SDR). See

Clock Enable Inputs - CE1 and CE2

Each ISERDES_NODELAY block contains an input clock enable module
X-Ref Target - Figure 8-4
When NUM_CE = 1, the CE2 input is not used, and the CE1 input is an active High clock
enable connected directly to the input registers in the ISERDES_NODELAY. When
NUM_CE = 2, the CE1 and CE2 inputs are both used, with CE1 enabling the
ISERDES_NODELAY for ½ of a CLKDIV cycle, and CE2 enabling the
ISERDES_NODELAY for the other ½. The internal clock enable signal ICE shown in
Figure 8-4
356
OSERDES
Data Bits
D1 Q
A
D2
B
D3
C
D4
D
D5
E
D6
F
CLKDIV_TX
Figure 8-3: Bit Ordering on Q1–Q6 Outputs of ISERDES_NODELAY Ports
"BITSLIP Submodule"
CE1 D Q
RST
AR
CLKDIV
CE2 D Q
RST
AR
CLKDIV
Figure 8-4: Input Clock Enable Module
is derived from the CE1 and CE2 inputs. ICE drives the clock enable inputs of
www.xilinx.com
F E D C B
CLK_TX CLK_RX
for more details.
CE1R
NUM_CE
1
2
CE2R
2
ISERDES
A
D Q1
Q2
Q3
Q4
Q5
Q6
CLKDIV_RX
UG190_8_03_100307
(Figure 8-4).
ICE
(To ISERDES Input Registers)
CLKDIV ICE
X CE1
0 CE2R
1 CE1R
UG190_8_04_110707
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
F
E
D
C
B
A