Lcd Panel Used In Character Mode - Xilinx Virtex-5 FPGA ML550 User Manual

R
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
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RData (8+gnd)
IorD = '1' Instruction
WData (32+4)
Address
Write
Enable
Clock
Block RAM
Clock
Reset
Design for Full Graphics Interface, Attached to CoreConnect Bus
Figure C-8: General Block Diagram of Panel in Full Graphics Mode

LCD Panel Used in Character Mode

This design example requires a byte representing a command or data to be displayed as
input.
•
When the Enable signal is Low, nothing happens. The display interface design is
locked.
•
When the Enable signal is High and the "data_or_command" control signal is Low,
the byte written is a display command.
•
When the Enable signal and the data_or_command control signal are High, the byte
written is the ASCII character code of the character to be put on the display.
Display Command Byte
The command set of the display can be found in
When the LCD interface is enabled for the first time, a set of command bytes is sent to the
LCD. This command set provides the basic initialization of the LCD display controller.
When this initialization is done, the normal LCD display interface is freed for normal use.
Command bytes from the valid command set can be sent to the display (controller).
A detailed description of the LCD controller interface can be found in the
Toplevel.vhd.txt file.
DataOut (8)
IorD (bit 9)
'0' Data
Addr
read
ena
Clock
E
TC
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Hardware Schematic Diagram
DataIn (8)
Clock
Reset
State
Machine
Clock
UG202_C_08_050906
Table C-7.
DB (8)
CS1B
RS
RW
E
81