Guidelines For Expanding The Serial-To-Parallel Converter Bit Width - Xilinx Virtex-5 FPGA User Manual

Chapter 8: Advanced SelectIO Logic Resources
X-Ref Target - Figure 8-7

Guidelines for Expanding the Serial-to-Parallel Converter Bit Width

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SERDES_MODE=MASTER
Data Input
D
SHIFTOUT1 SHIFTOUT2
SHIFTIN1
D
SERDES_MODE=SLAVE
Figure 8-7: Block Diagram of ISERDES Width Expansion
Both ISERDES modules must be adjacent master and slave pairs. Both ISERDES
modules must be in NETWORKING mode because width expansion is not available in
MEMORY mode.
Set the SERDES_MODE attribute for the master ISERDES to MASTER and the slave
ISERDES to SLAVE. See "SERDES_MODE Attribute."
The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the
MASTER.
The SLAVE only uses the ports Q3 to Q6 as an input.
DATA_WIDTH applies to both MASTER and SLAVE in
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Q1
Q2
ISERDES
Q3
(Master) Q4
Q5
Q6
SHIFTIN2
Q1
Q2
ISERDES
Q3
(Slave) Q4
Q5
Q6
Data_internal [0:5]
Data_internal [6:9]
ug190_8_07_100307
Figure 8-7.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009