Case 1: Writing To An Empty Fifo - Xilinx Virtex-5 FPGA User Manual

Case 1: Writing to an Empty FIFO

Prior to the operations performed in
X-Ref Target - Figure 4-21
Clock Event 1 and Clock Event 3: Write Operation and Deassertion of EMPTY
Signal
During a write operation to an empty FIFO, the content of the FIFO at the first address is
replaced by the data value on the DI pins. Three read-clock cycles later (four read-clock
cycles for FWFT mode), the EMPTY pin is deasserted when the FIFO is no longer empty.
The RDCOUNT also increments by one due to an internal read preloading the data to the
output registers.
For the example in
event 1 is with respect to the write-clock, while clock event 3 is with respect to the read-
clock. Clock event 3 appears four read-clock cycles after clock event 1.
•
•
•
•
If the rising WRCLK edge is close to the rising RDCLK edge, EMPTY could be deasserted
one RDCLK period later.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
1
WRCLK
WREN
DI
00
RDCLK
RDEN
DO
EMPTY
AEMPTY
Figure 4-21: Writing to an Empty FIFO in FWFT Mode
Figure 4-21, the timing diagram is drawn to reflect FWFT mode. Clock
At time T , before clock event 1 (WRCLK), data 00 becomes valid at the DI
FDCK_DI
inputs of the FIFO.
At time T , before clock event 1 (WRCLK), write enable becomes valid at
FCCK_WREN
the WREN input of the FIFO.
At time T , after clock event 3 (RDCLK), data 00 becomes valid at the DO
FCKO_DO
output pins of the FIFO. In standard mode, data 00 does not appear at the DO output
pins of the FIFO.
At time T , after clock event 3 (RDCLK), EMPTY is deasserted. In standard
FCKO_EMPTY
mode, EMPTY is deasserted one read-clock earlier than clock event 3.
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FIFO Timing Models and Parameters
Figure 4-21, the FIFO is completely empty.
T
FCCK_WREN
T
FDCK_DI
01 02
2 3 4
T
FDCK_DI
03 04 05
T
FCKO_DO
00
T
FCKO_EMPTY
T
FCKO_AEMPTY
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