Status Flags - Xilinx Virtex-5 FPGA User Manual

Status Flags

The example in
shift overflow and CLKIN/CLKFB/CLKFX failure.
X-Ref Target - Figure 2-20
CLKIN
CLKFB
CLKFX
DO(0)
DO(1)
DO(2)
PSCLK
PSEN
PSDONE
DO(3)
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Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Figure 2-20 shows the behavior of the status flags in the event of a phase-
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1
Figure 2-20: Status Flags Example
Clock Event 1
Prior to the beginning of this timing diagram, CLK0 (not shown) is already phase-
shifted at its maximum value. At clock event 1, PSDONE is asserted. However, since
the DCM has reached its maximum phase-shift capability no phase adjustment is
performed. Instead, the phase-shift overflow status pin DO(0) is asserted to indicate
this condition.
Clock Event 2
The CLKFX output stops toggling. Within 257 to 260 clock cycles after this event, the
CLKFX stopped status DO(2) is asserted to indicate that the CLKFX output stops
toggling.
Clock Event 3
The CLKFB input stops toggling. Within 257 to 260 clock cycles after this event, the
CLKFB stopped status DO(3) is asserted to indicate that the CLKFB output stops
toggling.
Clock Event 4
The CLKIN input stops toggling. Within 9 clock cycles after this event, DO(1) is
asserted to indicate that the CLKIN output stops toggling.
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3
257 - 260 Cycles
DCM Timing Models
4
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