Controller - Lcd Panel Connections - Xilinx Virtex-5 FPGA ML561 User Manual
Memory interfaces development board
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Table C-2: LCD Panel (Continued)
DB3 DB2 DB1 DB0 Data
DB0
DB1
DB2
DB3
0
1
1
0
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
0
1
1
1
DB4
DB5
DB6
DB7
DB0
1
0
0
0
ADC = 0
0
Column
83
Address
ADC = 1
LCD Output
When a page is addressed, all the bits representing dots on the LCD panel can be accessed
in that page. An array of 8x132 bits is available. The line address dictates what line of the
RAM is going to be displayed on the first line of the glass panel.
Controller – LCD Panel Connections
The controller die, KS0713, connects to the LCD glass panel and user connection pins via a
small PCB. Other necessary pins have default connections on the PCB.
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
1
2
3
4
5
6
7
82
81
80
7F
7
7
7
E
D
C
www.xilinx.com
Hardware Schematic Diagram
Page 6
Page 7
Page 8
8
9
A
B
7E
7
7
79
78
5
B
A
Line
Address
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
7F
80
81
82
83
4
3
2
1
0
125
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