Cpld Programming Examples; Static Configuration - Xilinx Virtex-5 FPGA ML555 User Manual

R
Table 4-5: Pin Listing for Platform Flash (Continued)
Pin
Net Name
Number
D2 Unused
D3 Unused
D4 Unused
E3 Unused
E4 Unused
F2 Unused
F3 Unused
F4 Unused
G2 Unused
Notes:
1. The ML555 board uses 2.5V I/O drivers for the JTAG chain. The Platform Flash V
of devices in the chain.

CPLD Programming Examples

Static Configuration

Figure 4-6
the FPGA to be statically selected and programmed with up to four bitstreams located in
the Flash. The selection of the bitstream is based on the configuration of the Flash Image
Select header P3.
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Direction Pin Type
O CEO
I DNC4
I DNC5
I DNC6
I DNC7
I DNC8
I DNC9
I DNC10
I DNC11
shows one possibility of connecting the FPGA to the Flash. This example allows
Table 4-6 shows the jumper settings for header P3.
www.xilinx.com
Description
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
connection should match JTAG I/O voltages
CCJ
SelectMAP Interface
97