Revision History - Xilinx Virtex-5 FPGA User Manual

Revision History

The following table shows the revision history for this document.
Date Version
04/14/06 1.0
05/12/06 1.1
7/19/06 1.2
9/06/06 2.0
10/12/06 2.1
UG190 (v5.0) June 19, 2009
Initial Xilinx release.
Minor typographical edits and clarifications.
Chapter 1: Revised Figure
Chapter 2: Revised Figure 2-2
primitive. Removed outdated clocking wizard section
Chapter 3: Revised Figure
and Figure 3-12. Added "PLL in Virtex-4 FPGA PMCD Legacy Mode"
Chapter 4: Added a note to
design rules on page 132.
Chapter 5: Added Figure 5-7
Chapter 6: Updated "Simultaneous Switching Output Limits"
Chapter 7: Revised "ILOGIC Resources," page 318
Table 7-3.
Chapter 8: Revised Table 8-1.
Chapter 1: Revised "Global Clock Buffers," page 27
Changed the P and N I/O designations in
Chapter 4: Added "Block RAM SSR in Register Mode," page 133
a Top-Level View," page 142. Revised the FIFO operations
Chapter 6: Minor clarification edits. Changed to N/A from unused in
Table 6-37, and Table 6-38.
Chapter 7: Minor edits to clarify IODELAY in this chapter.
Chapter 8: Small clarifications in
Added the LXT platform devices throughout document.
Chapter 1: Revised Figure 1-22, page
Chapter 2: Updated "Output Clocks" on page
Chapter 4: Clarified the rules regarding FULL and EMPTY flags on
Chapter 5: Revised "Storage Elements" on page
Chapter 6: "Differential Termination Attribute" on page 237
syntax and settings. Replaced the link to the SSO calculator.
Added System Monitor User Guide reference in the Preface.
Added XC5VLX85T to Table
Chapter 3: Revised Figure
Chapter 4: Added cascade to
Removed scrub mode in "Built-in Error Correction"
Chapter 5: Revised Figure 5-22, page
www.xilinx.com
Revision
1-21.
and Figure 2-4. Removed reference to a DCM_PS
3-1, Figure 3-2, Table 3-2, Table
Table 4-5, page 124. Clarified the RAMB36 port mapping
and Figure 5-11, revised
including
to clarify single-ended clock pins.
Figure 1-19.
"ISERDES_NODELAY Ports" on page
45. Updated "Clock Capable I/O" on page
65.
178.
1-5, Table 2-1, and Table
3-1.
Table 4-7, page 126. Revised ADDR in
section.
197.
page 83.
3-4, Figure 3-9, Equation
section.
Figure 5-32 for clarity.
section.
Figure 7-1. Revised
and "FIFO Architecture:
"Reset," page 144 description.
Table 6-36,
355.
page 139.
is updated for the latest
5-2.
Figure 4-9, page
Virtex-5 FPGA User Guide
3-8,
40.
124.