Top-Level View Of The Block Ram Ecc Architecture - Xilinx Virtex-5 FPGA User Manual

Chapter 4: Block RAM

Top-Level View of the Block RAM ECC Architecture

Figure 4-28
X-Ref Target - Figure 4-28
WRADDR[8:0]
RDADDR[8:0]
DIP[7:0]
ECCPARITY[7:0]
DI[63:0]
DO[63:0]
DBITERR
SBITERR
DOP[7:0]
160
shows the top-level view of a Virtex-5 FPGA block RAM in ECC mode.
wraddr
rdaddr
8
64-bit
64
ECC
Encode
DO_REG
EN_ECC_READ
0
64
1
Q D
DO_REG
0
1
1
Q D
DO_REG
0
1
1
Q D
DO_REG
0
1
8
1
Q D
0
EN_ECC_READ
Figure 4-28: Top-Level View of Block RAM ECC
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8
0
1
8
EN_ECC_WRITE
Data In
64
0
64 Data
1
Out
0
1
1
Decode
and
Correct
0
1
1
8
Parity
Out
8
9
9
8
64
Block RAM
512 x 72
64
8
UG190_c4_25_022609
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009