Fifo Vhdl And Verilog Templates; Fifo Timing Models And Parameters - Xilinx Virtex-5 FPGA User Manual

Similarly, the ALMOST_EMPTY flag can be used to stop reading. However, this would
make it impossible to read the very last entries remaining in the FIFO. The user can ignore
the Almost Empty signal and continue to read until EMPTY is asserted.
The Almost Full and Almost Empty offsets can also be used in unstoppable block transfer
applications to signal that a complete block of data can be written or read.
When setting the offset ranges in the design tools, use hexadecimal notation.

FIFO VHDL and Verilog Templates

VHDL and Verilog templates are available in the Libraries Guide.

FIFO Timing Models and Parameters

Table 4-20
Table 4-20: FIFO Timing Parameters
Parameter
Setup and Hold Relative to Clock (CLK)
T = Setup time (before clock edge)
RXCK
T = Hold time (after clock edge)
RCKX
T / Data inputs
RDCK_DI
(4)
T
RCKD_DI
T / Read enable
RCCK_RDEN
(5)
T
RCKC_RDEN
T / Write enable
RCCK_WREN
(5)
T
RCKC_WREN
Clock to Out Delays
(1)
T Clock to data output
RCKO_DO
(2)
T Clock to almost empty
RCKO_AEMPTY
output
(2)
T Clock to almost full
RCKO_AFULL
output
(2)
T Clock to empty output
RCKO_EMPTY
(2)
T Clock to full output
RCKO_FULL
(2)
T Clock to read error
RCKO_RDERR
output
(2)
T Clock to write error
RCKO_WRERR
output
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
shows the FIFO parameters.
Control
Function
Signal
DI
RDEN
WREN
DO
AEMPTY
AFULL
EMPTY
FULL
RDERR
WRERR
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FIFO VHDL and Verilog Templates
Description
Time before/after WRCLK that D1 must be stable.
Time before/after RDCLK that RDEN must be stable.
Time before/after WRCLK that WREN must be stable.
Time after RDCLK that the output data is stable at the
DO outputs of the FIFO. The synchronous FIFO with
DO_REG = 0 is different than in multirate mode.
Time after RDCLK that the Almost Empty signal is
stable at the ALMOSTEMPTY outputs of the FIFO.
Time after WRCLK that the Almost Full signal is
stable at the ALMOSTFULL outputs of the FIFO.
Time after RDCLK that the Empty signal is stable at
the EMPTY outputs of the FIFO.
Time after WRCLK that the Full signal is stable at the
FULL outputs of the FIFO.
Time after RDCLK that the Read Error signal is stable
at the RDERR outputs of the FIFO.
Time after WRCLK that the Write Error signal is stable
at the WRERR outputs of the FIFO.
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