Ddr2 Component Read Operation - Xilinx Virtex-5 FPGA ML561 User Manual
Memory interfaces development board
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DDR2 Component Read Operation
This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from the DDR2
memory component (U12) to FPGA1 (U7) measured at 333 MHz (667 Mb/s), where the
unit interval (UI) = 1.5 ns.
U12.D3
TL2
TL3
28.5 ohms
71.0 ohms
3.579 ps
27.482 ps
MT47H64M8CB-3
0.022 in
AutoPadstk_3
DQ3
DDR2_DQ_BY2_B3
DDR2_D...
22.9 fF
Figure 7-12: Post-Layout IBIS Schematics of the DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)
Table 7-4: Circuit Elements of DDR2 Component Read Data Bit
(DDR2_DQ_BY2_B3)
Table 7-5: DDR2 Component Read Operation Correlation Results
Measurement
Hardware at probe point
Simulation correlation
slow-weak corner
Correlation Delta:
HW vs. Simulation
Extrapolation at IOB
slow-weak corner
Extrapolation at IOB
fast-strong corner
To perform hardware measurements for a Read operation that is not interrupted by a Write
or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch
(SW2) setting:
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
TL4
TL8
49.0 ohms
58.3 ohms
24.721 ps
25.244 ps
0.164 in
AutoPadstk_19
DDR2_DQ_BY2_B3
DDR2_D...
DDR2_D...
C9
58.1 fF
22.9 fF
500.0 fF
Element
Driver
Receiver
Probe Point
PCB Termination
Trace Length
DVW (% UI)
(70 + 110) = 180 ps
1.28 ns
(85%)
(132 + 91) = 223 ps
1.28 ns
(85%)
0 ps
(0.0%)
(96 + 82) = 178 ps
1.29 ns
(86%)
(29 + 67) = 96 ps
1.32 ns
(88%)
DIP[1:2] = 2'b10 – Write once, then Read only, Refresh disabled
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Signal Integrity Correlation Results
TL9
TL6
49.1 ohms
49.1 ohms
47.132 ps
445.560 ps
0.302 in
2.852 in
DDR2_DQ_BY2_B3
DDR2_DQ_BY2_B3
DDR2_D...
DDR2_D...
140.8 fF
365.6 fF
Designation
U12.D3
DDR2 Memory
U7.P25
FPGA SSTL18_II_DCI_I
C7
Via under FPGA1
None
DCI at receiver
TL 2, 4, 9, 6, 1
3.37 inches
Noise Margin
ISI
(VIH + VIL) = Total
(% UI)
(% of VREF)
(423 + 416) = 839 mV
(12%)
(83.1%)
(406 +439) = 845 mV
(14.9%)
(83.8%)
43 ps
6 mV
(2.9%)
(0.7%)
(418 + 449) = 867 mV
(11.9%)
(96.3%)
(455 +435) = 890 mV
(6.7%)
(98.9%)
TL5
TL1
28.5 ohms
21.2 ohms
Virtex-5 FPGA
1.000 ps
4.473 ps
DDR2_DQ_BY2_B3
AutoPadstk_3
0.028 in
DDR2_DQ_BY2_B3
DDR2_D...
C7
22.9 fF
500.0 fF
UG199_c7_12_071907
Description
Overshoot /
Undershoot Margin
(% of VREF)
(400 +400) = 800 mV
(79.1%)
(279 +277) = 556 mV
(61.9%)
244 mV
(17.2%)
(304 +265) = 569 mV
(63.1%)
(167 +182) = 349 mV
(38.9%)
U7.P25
65
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