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Xilinx Virtex-5 FPGA User Manual

Xilinx Virtex-5 FPGA User Manual

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Virtex-5 FPGA
User Guide
UG190 (v5.0) June 19, 2009

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  • Page 1 Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Revision History

    Chapter 4: Added cascade to Table 4-7, page 126. Revised ADDR in Figure 4-9, page 124. Removed scrub mode in “Built-in Error Correction” section. Chapter 5: Revised Figure 5-22, page 197. UG190 (v5.0) June 19, 2009 www.xilinx.com Virtex-5 FPGA User Guide...
  • Page 4 Chapter 8: Updated SR and O in Figure 8-2 Table 8-1, page 355. Updated the entire section for “BITSLIP Submodule,” page 366. Fixed typographical errors in Figure 8-14, page 370. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 5 Updated CLKOUT[0:5]_DESKEW_ADJUST description in Table 3-4, page Revised equations Equation 3-5 Equation 3-6. Updated the notes in Table 4-16, page 145. Revised description of “Instantiating IDELAYCTRL with Location (LOC) Constraints,” page 342. UG190 (v5.0) June 19, 2009 www.xilinx.com Virtex-5 FPGA User Guide...
  • Page 6 Chapter 7: In the Verilog code segment for bidirectional IODELAY on page 333, corrected the setting of RST. 03/19/09 Chapter 3: Added reference to the Virtex-5 FPGA Configuration Guide in “PLL_ADV Primitive,” page Chapter 4: In the second paragraph of “Write Modes,” page 117, added “in ECC...
  • Page 7 Chapter 2: Updated Dynamic Reconfiguration description in “DCM Summary,” page 48 to remove “different phase shift” as an attribute changeable via dynamic reconfiguration. Chapter 3: Updated definition of LOCKED pin in Table 3-3, page UG190 (v5.0) June 19, 2009 www.xilinx.com Virtex-5 FPGA User Guide...
  • Page 8 Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 9: Table Of Contents

    ......... . 52 Phase-Shift Clock Input - PSCLK Virtex-5 FPGA User Guide www.xilinx.com...
  • Page 10 ..........68 Phase-Shifting Operation www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 11 Missing Input Clock or Feedback Clock ........105 Virtex-5 FPGA User Guide www.xilinx.com...
  • Page 12 Content Initialization - INITP_xx ......... . 129 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 13 ........149 Virtex-5 FPGA User Guide www.xilinx.com...
  • Page 14 ..........203 Timing Characteristics Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only)204 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 15 IOBUFDS ............. . . 236 Virtex-5 FPGA SelectIO Attributes/Constraints ......236 .
  • Page 16 ........237 Differential Termination Attribute Virtex-5 FPGA I/O Resource VHDL/Verilog Examples ..... . . 238 Specific Guidelines for I/O Supported Standards .
  • Page 17 ........325 Virtex-5 FPGA User Guide www.xilinx.com...
  • Page 18 ISERDES Timing Model and Parameters ........363 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 19 ................383 Virtex-5 FPGA User Guide www.xilinx.com...
  • Page 20 Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 21: Preface: About This Guide

    Preface About This Guide This document describes the Virtex®-5 architecture. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5. Additional Documentation The following documents are also available for download at http://www.xilinx.com/virtex5.

  • Page 22: Additional Support Resources

    To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. Typographical Conventions This document uses the following typographical conventions. An example illustrates each convention.

  • Page 23: Online Document

    Blue text Refer to “Clock Management in the current document Technology” in Chapter 2 details. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest documentation. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 24 Preface: About This Guide www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 25: Chapter 1: Clock Resources

    A third type of clocking resource, I/O clocks, are very fast and serve localized I/O serializer/deserializer circuits. See Chapter 8, “Advanced SelectIO Logic Resources.” Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 26: Global Clocking Resources

    Input clock buffer for single-ended I/O IBUFGDS I, IB Input clock buffer for differential I/O These two primitives work in conjunction with the Virtex-5 FPGA I/O resource by setting the IOSTANDARD attribute to the desired standard. Refer to Chapter 6, “I/O Compatibility” Table 6-39 for a complete list of possible I/O standards.

  • Page 27: Global Clock Buffers

    The clock buffers are designed to be configured as a synchronous or asynchronous glitch- free 2:1 multiplexer with two clock inputs. Virtex-5 FPGA control pins provide a wide range of functionality and robust input switching. The following subsections detail the various configurations, primitives, and use models of the Virtex-5 FPGA clock buffers.

  • Page 28: Global Clock Buffer Primitives

    BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control lines, IGNORE0 and IGNORE1. These six control lines are used to control the input I0 and X-Ref Target - Figure 1-1 BUFGCTRL IGNORE1 IGNORE0 ug190_1_01_032206 Figure 1-1: BUFGCTRL Primitive www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 29 Setup/Hold times. It will not result in a glitch. See “BUFGMUX_CTRL.” The CE pin is designed to allow backward compatibility from Virtex- II and Virtex-II Pro FPGAs. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 30 Clock selection using CE0 and CE1 only (S0 and S1 tied High) can change the clock selection without waiting for a High to Low transition on the previously selected clock. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 31 Figure 1-3: BUFG as BUFGCTRL The output follows the input as shown in the timing diagram in Figure 1-4. X-Ref Target - Figure 1-4 BUFG(I) BUFG(O) BCCKO_O ug190_1_04_032206 Figure 1-4: BUFG Timing Diagram Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 32 Low pulse has no effect until the clock transitions High. The output stays High when the clock is disabled. However, when the clock is being disabled it completes the clock Low pulse. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 33 Violating this setup time might result in a glitch. Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL. Figure 1-9 illustrates the timing diagram for BUFGMUX. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 34 Once I0 is High, the multiplexer output stays High until I1 transitions Low to High. • When I1 transitions from Low to High, the output switches to I1. • If Setup/Hold are met, no glitches or short pulses can appear on the output. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 35 Figure 1-12: BUFGMUX_CTRL Timing Diagram Other capabilities of the BUFGMUX_CTRL primitive are: • Pre-selection of I0 and I1 input after configuration. • Initial output can be selected as High or Low after configuration. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 36: Additional Use Models

    The current clock is from I0. • S is activated High. • The Clock output immediately switches to I1. • When Ignore signals are asserted High, glitch protection is disabled. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 37 , before time event 3, CE is asserted Low. The clock output is BCCCK_CE switched Low and kept at Low after a High to Low transition of I1 is completed. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 38: Clock Tree And Nets - Gclk

    All clock regions are 20 CLBs tall (10 CLBs above and 10 CLBs below a horizontal clock line) Center Column Logic Resources ug190_1_17_042406 Figure 1-17: Clock Regions www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 39 Global Clocking Resources Table 1-5: Virtex-5 FPGA Clock Regions Device Number of Clock Regions Notes XC5VLX30 XC5VLX50 XC5VLX85 XC5VLX110 XC5VLX155 XC5VLX220 XC5VLX330 XC5VLX20T There are 3 regions on each side of the device. There are no BUFRs on the right side of this device.

  • Page 40: Regional Clocking Resources

    When used as single-ended clock pins, then as described in “Global Clock Buffers,” the P-side of the pin pair must be used because a direct connection only exists on this pin. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 41: I/O Clock Buffer - Bufio

    1-19, a BUFIO is used to drive the I/O logic using the clock capable I/O. This implementation is ideal in source-synchronous applications where a forwarded clock is used to capture incoming data. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 42: Regional Clock Buffer - Bufr

    Regional Clock Buffer - BUFR The regional clock buffer (BUFR) is another clock buffer available in Virtex-5 devices. BUFRs drive clock signals to a dedicated clock net within a clock region, independent from www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 43: Bufr Primitive

    (GSR) signal is High, BUFR does not toggle, even if CE is held High. The BUFR output toggles after the GSR signal is deasserted when a clock is on the BUFR input port. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 44: Bufr Attributes And Modes

    • At time event 3, CLR is deasserted. • At time T after clock event 4, O begins toggling again at the divided by three BRCKO_O rate of I. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 45: Bufr Use Models

    I/O Tile Block Tile CLBs I/O Tile Clock Capable I/O CLBs I/O Tile BUFIO BUFR To Center of Die To Region Below UG190_c1_22_022609 Figure 1-22: BUFR Driving Various Logic Resources Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 46: Regional Clock Nets

    Figure 1-23: BUFR Driving Multiple Regions VHDL and Verilog Templates The VHDL and Verilog code for all clocking resource primitives and ISE language templates are available in the Libraries Guide. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 47: Chapter 2: Clock Management Technology

    Virtex-5 FPGA Config Blocks and Center Column BUFGs Config I/O (Bottom Half) Clock I/O (Bottom Half) CMT Blocks (Bottom Half DCMs/PLLs) I/O Banks (Larger Devices Only) UG190_c2_01_022609 Figure 2-1: CMT Location Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 48: Dcm Summary

    (CLKIN) against a feedback input (CLKFB) and steers the delay line selector, essentially adding delay to the output of DCM until the CLKIN and CLKFB coincide. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 49 The user can specify any integer multiplier (M) and divisor (D) within the range specified in the DCM Timing Parameters section of the Virtex-5 FPGA Data Sheet. An internal calculator determines the appropriate tap selection, to make the output edge coincide with the input clock whenever mathematically possible.

  • Page 50: Dcm Primitives

    Table 2-2: DCM_BASE Primitive Available Ports Port Names Clock Input CLKIN, CLKFB Control and Data Input Clock Output CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV, CLKFX, CLKFX180 Status and Data Output LOCKED www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 51: Dcm_Adv Primitive

    Source Clock Input - CLKIN The source clock (CLKIN) input pin provides the source clock to the DCM. The CLKIN frequency must fall in the ranges specified in the Virtex-5 FPGA Data Sheet. The clock input signal comes from one of the following buffers: IBUFG –...

  • Page 52: Feedback Clock Input - Clkfb

    BUFGCTRL – An Internal Global Buffer Internal Clock – Any internal clock using general purpose routing. The frequency range of PSCLK is defined by PSCLK_FREQ_LF/HF. See the Virtex-5 FPGA Data Sheet. This input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED.

  • Page 53: Dynamic Reconfiguration Clock Input - Dclk

    CLKIN signal is present and stable for at least three CLKIN cycles. The time it takes for the DCM to lock after a reset is specified in the Virtex-5 FPGA Data Sheet as LOCK_DLL (for a DLL output) and LOCK_FX (for a DFS output). These are the CLK and CLKFX outputs described in “DCM Clock Output Ports.”...

  • Page 54: Phase-Shift Enable Input - Psen

    The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low. See the Dynamic Reconfiguration chapter of the Virtex-5 FPGA Configuration Guide for more information.

  • Page 55: 1X Output Clock, 90° Phase Shift - Clk90

    CLKFX_MULTIPLY attribute. D is the divisor (denominator) with a value defined by the CLKFX_DIVIDE attribute. Specifications for M and D, as well as input and output frequency ranges for the frequency synthesizer, are provided in the Virtex-5 FPGA Data Sheet.

  • Page 56: Dcm Status And Data Output Ports

    After a reset, the DCM samples several thousand clock cycles to achieve lock. After the DCM achieves lock, the LOCKED signal is asserted High. The DCM timing parameters section of the Virtex-5 FPGA Data Sheet provides estimates for locking times.

  • Page 57: Dynamic Reconfiguration Ready Output - Drdy

    The dynamic reconfiguration ready (DRDY) output pin provides the response to the DEN signal for the DCM’s dynamic reconfiguration feature. Further information on the DRDY pin is available in the dynamic reconfiguration section in the Virtex-5 FPGA Configuration Guide. Virtex-5 FPGA User Guide www.xilinx.com...

  • Page 58: Dcm Attributes

    CLKIN_PERIOD Attribute The CLKIN_PERIOD attribute specifies the source clock period (in nanoseconds). The default value is 0.0 ns. Setting this attribute to the input period values produces the best results. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 59: Clkin_Divide_By_2 Attribute

    When set to DIRECT, the DCM output can be phase-shifted in variable mode in the positive range with respect to CLKIN. Each phase-shift increment/decrement will increase/decrease the phase shift by one DCM_TAP. See the Virtex-5 FPGA Data Sheet. The starting phase in the VARIABLE_POSITIVE and VARIABLE_CENTER modes is determined by the phase-shift value.

  • Page 60: Deskew_Adjust Attribute

    FALSE. The default value is TRUE. When set to TRUE, the 1x clock outputs are duty cycle corrected to be within specified limits. See the Virtex-5 FPGA Data Sheet for details. It is strongly recommended to always set the DUTY_CYCLE_CORRECTION attribute to TRUE.

  • Page 61: Factory_Jf Attribute

    This attribute allows for the input Boolean: FALSE or TRUE FALSE clock frequency to be divided in half when such a reduction is necessary to meet the DCM input clock frequency requirements. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 62 CLKOUT_PHASE_SHIFT and clock frequency. STARTUP_WAIT When this attribute is set to TRUE, Boolean: FALSE or TRUE FALSE the configuration startup sequence waits in the specified cycle until the DCM locks. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 63: Dcm Design Guidelines

    Adjust”) is available to compensate for the clock source or feedback path. The Xilinx ISE tools analyze the routing around the DCM to determine if a delay must be inserted to compensate for the clock source or feedback path. Thus, using dedicated routing is required to achieve predictable deskew.

  • Page 64: Input Clock Requirements

    The DCM output clock signal is essentially a delayed version of the input clock signal. It reflects any instability on the input clock in the output waveform. The DCM input clock requirements are specified in the Virtex-5 FPGA Data Sheet. Once locked, the DCM can tolerate input clock period variations of up to the value specified by CLKIN_PER_JITT_DLL_HF (at high frequencies) or CLKIN_PER_JITT_DLL_LF (at low frequencies).

  • Page 65: Output Clocks

    DCM not locking and an incomplete configuration. Deskew Adjust The DESKEW_ADJUST attribute sets the value for a configurable, variable-tap delay element to control the amount of delay added to the DCM feedback path (see Figure 2-4). Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 66 DCMINO includes tap delays in the default setting (red line). The pin-to-pin timing parameters (with DCM) on the Virtex-5 FPGA Data Sheet reflects the setup/hold and clock-to-out times when the DCM is in system-synchronous mode. In some situations, the DCM does not add this extra feedback delay, and the DESKEW_ADJUST parameter has no effect.

  • Page 67: Characteristics Of The Deskew Circuit

    Characteristics of the Deskew Circuit • Eliminate clock distribution delay by effectively adding one clock period delay. • Clocks are deskewed to within CLKOUT_PHASE, specified in the Virtex-5 FPGA Data Sheet. • Eliminate on-chip as well as off-chip clock delay.

  • Page 68: Frequency Synthesizer Characteristics

    The internal operation of the frequency synthesizer is complex and beyond the scope of this document. As long as the frequency synthesizer is within the range specified in the Virtex-5 FPGA Data Sheet, it multiplies the incoming frequencies by the pre-calculated quotient M ÷ D and generates the correct output frequencies.
  • Page 69 Total delay is a function of the number of delay taps used in the circuit. The absolute range is specified in the DCM Timing Parameters section of the Virtex-5 FPGA Data Sheet across process, voltage, and temperature. The different absolute ranges are outlined in this section.
  • Page 70 All phase-shift modes, with the exception of DIRECT mode, are temperature and voltage adjusted. Hence, a V or temperature adjustment does not change the phase shift. The DIRECT phase shift is not temperature or voltage adjusted since it directly controls www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 71: Interaction Of Psen, Psincdec, Psclk, And Psdone

    PHASE_SHIFT, the PSDONE is still pulsed High for one PSCLK period some time after the PSEN is activated (as illustrated in Figure 2-6). However, the phase-shift overflow pin, STATUS(0), or DO(0) is High to flag this condition, and no phase adjustment is performed. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 72: Phase-Shift Overflow

    The phase-shifting (DPS) function in the DCM requires the CLKFB for delay adjustment. Because CLKFB must be from CLK0, the DLL output is used. The minimum CLKIN frequency for the DPS function is determined by DLL frequency mode. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 73: Dynamic Reconfiguration

    The Dynamic Reconfiguration Ports (DRPs) can update the initial DCM settings without reloading a new bit stream to the FPGA. The DRP address mapping changed in Virtex-5 FPGAs. The Virtex-5 FPGA Configuration Guide provides more information on using DRPs. Specific to the DCM, DRPs allow dynamic adjustment of the CLKFX_MULTIPLY(M) and CLKFX_DIVIDE(D) values to produce a new CLKFX frequency.

  • Page 74: Pll To And From Dcm

    The PMCD block is not available in the Virtex-5 devices. However, a limited retargeting using the PLL is possible. Refer to “PLL in Virtex-4 FPGA PMCD Legacy Mode” in Chapter 3 for more information. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 75: Application Examples

    Application Examples Application Examples The Virtex-5 FPGA DCM can be used in a variety of creative and useful applications. The following examples show some of the more common applications. Standard Usage The circuit in Figure 2-8 shows DCM_BASE implemented with internal feedback and access to RST and LOCKED pins.
  • Page 76 DCM_ADV BUFG IBUFG CLK0 CLKIN CLK90 CLK180 CLKFB CLK270 CLK2X CLK2X180 CLKDV CLKFX PSINCDEC CLKFX180 PSEN PSCLK DADDR[6:0] LOCKED DI[15:0] DO(15:0) DCLK ug190_2_11_032506 Figure 2-10: Board-Level Clock with Internal Feedback www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 77: Board Deskew With Internal Deskew

    These applications can be implemented using two or more DCM. The circuit shown in Figure 2-11 can be used to deskew a system clock between multiple Virtex devices in the same system. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 78 This circuit can be duplicated to multiple Virtex devices. Use CLKDLL for Virtex and Virtex-E devices, DCM for Virtex-II and Virtex-II Pro devices. ug190_2_12_032506 Figure 2-11: Board Deskew with Internal Deskew Interfacing to Other Virtex Devices www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 79 CLK180 CLKFB CLK270 CLK2X CLK2X180 CLKDV PSINCDEC CLKFX PSEN CLKFX180 PSCLK DADDR[6:0] DI[15:0] LOCKED DCLK DO[15:0] ...non-Virtex chips ug190_2_13_032506 Figure 2-12: Board Deskew with Internal Deskew Interfacing to Other Components Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 80: Clock Switching Between Two Dcms

    IBUFG DCM_ADV BUFG CLKIN CLK0 CLK90 CLK180 CLKFB CLK270 CLK2X CLK2X180 CLKDV PSINCDEC CLKFX PSEN CLKFX180 PSCLK DADDR[6:0] DI[15:0] LOCKED DO(15:0) DCLK ug190_2_14_032506 Figure 2-13: Clock Switching Between Two DCMs www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 81: Dcm With Pll

    X-Ref Target - Figure 2-14 IBUFG CLKIN1 CLKOUT0 CLKOUT1 CLKFBIN CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT BUFG CLKIN CLK0 CLK90 CLKFBIN CLK180 BUFG CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 ug190_2_15_040906 Figure 2-14: PLL Driving DCM Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 82 CLKIN CLK0 CLK90 CLKFBIN CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 BUFG CLKIN1 CLKOUT0 CLKOUT1 CLKFBIN CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT ug190_2_16_040906 Figure 2-15: Direct Connection between DCM and PLL www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 83: Vhdl And Verilog Templates, And The Clocking Wizard

    In addition, VHDL and Verilog files are generated by the Clocking Wizard in the ISE software. The Clocking Wizard sets appropriate DCM attributes, input/output clocks, and buffers for general use cases. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 84: Dcm Timing Models

    2, the lock process begins. At time LOCK_DLL, after clock event 2, if no fixed phase shift was selected then all clock outputs are stable and in phase. LOCKED is also asserted to signal completion. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 85: Fixed-Phase Shifting

    CLKIN. However, CLK0, and CLK2X are aligned to each other, while CLK90 and CLK180 remain as 90° and 180° versions of CLK0. The LOCK signal is also asserted once the clock outputs are ready. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 86: Variable-Phase Shifting

    DCM outputs. PSDONE is High for exactly one clock period when the phase shift is complete. The time required for a complete phase shift varies. As a result, PSDONE must be monitored for phase-shift status. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 87: Status Flags

    CLKFB stopped status DO(3) is asserted to indicate that the CLKFB output stops toggling. • Clock Event 4 The CLKIN input stops toggling. Within 9 clock cycles after this event, DO(1) is asserted to indicate that the CLKIN output stops toggling. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 88: Legacy Support

    Refer to the Virtex-5 FPGA Configuration Guide for more information. The Virtex-5 device supports the Virtex-II family and Virtex-II Pro FPGA DCM primitives. The mapping of Virtex-II or Virtex-II Pro FPGA DCMs to Virtex-5 FPGA DCM_ADVs are as follows: •...

  • Page 89: Chapter 3: Phase-Locked Loops (Plls)

    A DCM can not be inserted in the feedback path of the PLL. Both the PLLs or DCMs of a CMT can be used separately as stand-alone functions. The outputs from the PLL are not spread spectrum. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 90: Phase Locked Loop (Pll)

    DCM2 implementation UG190_c3_01_022709 Figure 3-1: Block Diagram of the Virtex-5 FPGA CMT Phase Locked Loop (PLL) Virtex-5 devices contain up to six CMT tiles. The PLLs main purpose is to serve as a frequency synthesizer for a wide range of frequencies, and to serve as a jitter filter for either external or internal clocks in conjunction with the DCMs of the CMT.
  • Page 91 Lock Detect Clock Lock Switch Lock Monitor Circuit 8-phase taps CLKIN1 CLKIN2 CLKFBOUT CLKFB VCO feedback phase selection for negative phase-shift affecting all outputs UG190_c3_03_022709 Figure 3-3: Detailed PLL Block Diagram Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 92: General Usage Description

    Chapter 3: Phase-Locked Loops (PLLs) General Usage Description PLL Primitives Figure 3-4 shows the two Virtex-5 FPGA PLL primitives, PLL_BASE and PLL_ADV. X-Ref Target - Figure 3-4 CLKIN1 CLKOUT0 CLKIN1 CLKOUT0 CLKOUT1 CLKIN2 CLKOUT1 CLKOUT2 CLKFBIN CLKOUT2 CLKFBIN CLKOUT3 CLKOUT3...

  • Page 93: Pll_Adv Primitive

    1. REL is used in PMCD mode only. In PLL mode, leave REL unconnected or tied Low. The Virtex-5 FPGA PLL is a mixed signal block designed to support clock network deskew, frequency synthesis, and jitter reduction. These three modes of operation are discussed in more detail within this section.

  • Page 94: Jitter Filter

    VCO operation range, input frequency, duty cycle programmability, and phase shift. VCO Operating Range The minimum and maximum VCO operating frequencies are defined in the electrical specification of the Virtex-5 FPGA Data Sheet. These values can also be extracted from the speed specification. Minimum and Maximum Input Frequency The minimum and maximum CLKIN input frequency are defined in the electrical specification of the Virtex-5 FPGA Data Sheet.

  • Page 95: Phase Shift

    The desired output frequency should be checked against the possible output frequencies generated. Once the first output frequency is determined, an additional constraint can be imposed on the values of M and D. This can further limit the Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 96: Determine The M And D Values

    A reset is required when the input clock conditions change (e.g., frequency). The dynamic reconfiguration address (DADDR) input bus provides a DADDR[4:0] Input reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 97 The dynamic reconfiguration ready output (DRDY) provides the response to the DRDY Output DEN signal for the PLLs dynamic reconfiguration feature. Notes: 1. CLKOUT and CLKOUTDCM are utilizing the same output counters and can not be operated independently. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 98: Pll Attributes

    CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency. DIVCLK_DIVIDE Integer 1 to 52 Specifies the division ratio for all output clocks with respect to the input clock. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 99 PPC440 system. See UG200: Embedded Processor Block in Virtex-5 FPGAs Reference Guide for details. RESET_ON_LOSS String FALSE FALSE Must be set to FALSE, not supported _OF_LOCK in silicon. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 100: Pll Clkin1 And Clkin2 Usage

    BUFG is not possible. The following tables map the Virtex-5 FPGA global clock IBUFG pins with respect to CLKIN1 and CLKIN2. PLLs in the top half of the Virtex-5 device are driven by the global...

  • Page 101: Pll Clock Input Signals

    An IBUF clock input must route to a BUFG before routing to a PLL. • DCMOUT - Any DCM output to PLL will compensate the delay of this path. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 102: Counter Control

    DUTY_CYCLE = 0.5 PHASE = 360 DIVIDE = 3 DUTY_CYCLE = 0.33 PHASE = 0 DIVIDE = 3 DUTY_CYCLE = 0.5 PHASE = 0 UG190_3_06_041406 Figure 3-6: Output Counter Clock Synthesis Examples www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 103: Clock Shifting

    PLL. When an important aspect of the design is to maintain a certain phase relationship amongst various clock outputs, (e.g., CLK and CLK90) then this relationship will be maintained regardless of the input frequency. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 104: Reference Clock Switching

    3-9. The CLKINSEL (CLKSRC) signal directly controls the mux. No synchronization logic is present. X-Ref Target - Figure 3-9 CLKSRC BUFG IBUFG CLKIN1 CLKIN BUFG IBUFG CLKIN2 ug190_3_09_050906 Figure 3-9: Input Clock Switching www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 105: Missing Input Clock Or Feedback Clock

    O = 2. The VCO frequency in this case is 500 MHz and the O output frequency is 250 MHz. Therefore, the feedback frequency at the PFD is 500/15 or 33.33 MHz, matching the 66.66MHz/2 input clock frequency at the PFD. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 106: Pll With Internal Feedback

    X-Ref Target - Figure 3-12 IBUFG OBUF BUFG Inside FPGA CLKIN1 CLKOUT0 External CLKOUT1 Components CLKFBIN CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 BUFG CLKFBOUT UG190_3_12_120108 Figure 3-12: Zero Delay Buffer www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 107: Dcm Driving Pll

    CLK90 CLKFBIN CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 BUFG CLKOUT0 CLKIN1 Matches To Logic, etc. CLKOUT1 CLKFBIN CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT ug190_3_13_092107 Figure 3-13: DCM Driving a PLL Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 108: Pll Driving Dcm

    CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT Matches BUFG CLKIN CLK0 To Logic, etc. CLKFBIN CLK90 CLK190 CLK270 To Logic, etc. CLK2X CLK2X190 CLKDV CLKFX CLKFX180 ug190_3_14_092107 Figure 3-14: PLL Driving a DCM www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 109: Pll To Pll Connection

    This section summarizes when to select a DCM over a PLL, or a PLL over a DCM. Virtex-5 FPGA PLLs support up to six independent outputs. Designs using several different outputs should use PLLs. An example of designs using several different outputs follows.

  • Page 110: Pll Application Example

    DIVCLK_DIVIDE = 1; CLKIN1_PERIOD = 10.0; Figure 3-16 displays the resulting waveforms. X-Ref Target - Figure 3-16 REFCLK VCOCLK CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 UG190_3_19_032506 Figure 3-16: Example Waveform www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 111: Pll In Virtex-4 Fpga Pmcd Legacy Mode

    Virtex-5 FPGA PLL, Xilinx recommends redesigning Virtex-4 FPGA PMCDs by implementing PLLs directly. The difference between the Virtex-5 FPGA PLL and the Virtex-4 FPGA PMCD block in Virtex-4 FPGA PMCD legacy mode is that only two clock inputs are supported in the Virtex-5 device implementation.
  • Page 112 Virtex-4 FPGA PMCD legacy mode CLKA1. CLKOUT2 Output Virtex-4 FPGA PMCD legacy mode CLKA1D2. CLKOUT3 Output Virtex-4 FPGA PMCD legacy mode CLKA1D4. CLKOUT4 Output Virtex-4 FPGA PMCD legacy mode CLKA1D8. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 113: Chapter 4: Block Ram

    Virtex-5 FPGA block RAM enhancements include: • Increased memory storage capability per block. Each block RAM can store up to 36K bits of data.
  • Page 114 The output data path has an optional internal pipeline register. Using the register mode is strongly recommended. This allows a higher clock rate, however, it adds a clock cycle latency of one. Virtex-5 FPGA block RAM usage rules: • The Synchronous Set/Reset (SSR) port cannot be used when the ECC decoder is enabled (EN_ECC_READ = TRUE).

  • Page 115: Block Ram Introduction

    Embedded dual- or single-port RAM modules, ROM modules, synchronous FIFOs, and data width converters are easily implemented using the Xilinx CORE Generator™ block memory modules. Multirate FIFOs can be generated using the CORE Generator FIFO Generator module.
  • Page 116 Data Output Parity Bus, can be used for additional data outputs REGCE[A|B] Output Register Enable CASCADEINLAT[A|B] Cascade input pin for 64K x 1 mode when optional output registers are not enabled www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 117: Read Operation

    For the simple dual port block RAM and ECC configurations, the Write mode is always READ_FIRST, and therefore no collision can occur when used in synchronous mode. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 118: Write_First Or Transparent Mode (Default)

    4-4, data output remains the last read data and is unaffected by a write operation on the same port. These waveforms correspond to latch mode when the optional output pipeline register is not used. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 119: Conflict Avoidance

    Figure 4-4: NO_CHANGE Mode Waveforms Conflict Avoidance Virtex-5 FPGA block RAM memory is a true dual-port RAM where both ports can access any memory location at any time. When accessing the same memory location from both ports, the user must, however, observe certain restrictions. There are two fundamentally different situations: The two ports either have a common clock (synchronous clocking), or the clock frequency and phase is different for the two ports (asynchronous clocking).

  • Page 120: Additional Block Ram Features In Virtex-5 Devices

    Independent Read and Write port width selection increases the efficiency of implementing a content addressable memory (CAM) in block RAM. This option is available for all Virtex-5 FPGA true dual-port RAM port sizes and modes. www.xilinx.com Virtex-5 FPGA User Guide...

  • Page 121: Simple Dual-Port Block Ram

    Read Data Clock RDEN Read Port Enable REGCE Output Register Clock Enable Synchronous Set/Reset Byte-wide Write Enable WRADDR Write Data Address Bus WRCLK Write Data Clock WREN Write Port Enable Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 122: Cascadable Block Ram

    “Additional RAMB18 and RAMB36 Primitive Design Considerations” section. Figure 4-8 shows the byte-wide write-enable timing diagram for the RAMB36. Table 4-4: Available Byte-wide Write Enables Primitive Maximum Bit Width Number of Byte-wide Write Enables RAMB36 RAMB36SDP www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 123: Block Ram Error Correction Code

    RAM data read out. Single-bit errors are then corrected in the output data. Block RAM Library Primitives The Virtex-5 FPGA block RAM library primitives, RAMB18 and RAMB36, are the basic building blocks for all block RAM configurations. Other block RAM primitives and macros are based on these primitives.
  • Page 124 CASCADEINLATA CASCADEINLATB CASCADEINREGA CASCADEINREGB ug0190_4_10_100906 Figure 4-9: Block RAM Port Signals (RAMB36) Table 4-5: Virtex-5 FPGA Block RAM, FIFO, Simple Dual Port, and ECC Primitives Primitive Description RAMB36 Supports port widths of x1, x2, x4, x9, x18, x36 RAMB36SDP Simple dual port (port width x72) and 64-bit ECC primitive (see...

  • Page 125: Block Ram Port Signals

    The address bus selects the memory cells for read or write. The data bit width of the port determines the required address bus width for a single RAMB18 or RAMB36, as shown in Table 4-6 Table 4-7. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 126: Data-In Buses - Di[A|B]<#:0> & Dip[A|B]<#:0

    The regular data-out bus (DO) plus the parity data-out bus (DOP) (when available) have a total width equal to the port width, as shown in Table 4-6 Table 4-7. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 127: Cascade In - Cascadeinlat[A|B] And Cascadeinreg[A|B]

    A GSR signal has no impact on internal memory contents. Because it is a global signal, the GSR has no input pin at the functional level (block RAM primitive). Unused Inputs Unused data and/or address inputs should be connected High. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 128: Block Ram Address Mapping

    = conversion hex-encoded to decimal (xx) “1F” = 31 • from [(31+1) × 256] – 1 = 8191 • to 31 × 256 = 7936 More examples are given in Table 4-9. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 129: Content Initialization - Initp_Xx

    4-10. These attributes are hex- encoded bit vectors, and the default value is 0. In cascade mode, both the upper and lower block RAM should be initialized to the same value. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 130: Output Latches/Registers Synchronous Set/Reset (Srval_[A|B])

    This attribute determines the write mode of the A/B input ports. The possible values are WRITE_FIRST (default), READ_FIRST, and NO_CHANGE. Additional information on the write modes is in the “Write Modes” section. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 131: Block Ram Location Constraints

    The Virtex-5 FPGA Libraries Guide includes the code to instantiate the RAMB36 primitive. Additional RAMB18 and RAMB36 Primitive Design Considerations The RAMB18 and RAMB36 primitives are integral in the Virtex-5 FPGA block RAM solution. Optional Output Registers Optional output registers can be used at either or both A|B output ports of RAMB18 and RAMB36.

  • Page 132: Ramb18 And Ramb36 Port Mapping Design Rules

    When using these attributes, if both write ports or both read ports are set to 0, the Xilinx ISE tools will not implement the design. In simple dual-port mode, the port width is fixed and the read port width is equal to the write port width. The RAMB18 has a data port width of 36, while the RAMB36 has a data port width of 72.

  • Page 133: Additional Block Ram Primitives

    RAMs with minimal routing delays. Wider or deeper RAM structures are achieved with a smaller timing penalty than is encountered when using normal routing resources. The Xilinx CORE Generator program offers the designer an easy way to generate wider and deeper memory structures using multiple block RAM instances. This program outputs VHDL or Verilog instantiation templates and simulation models, along with an EDIF file for inclusion in a design.

  • Page 134: Block Ram Timing Model

    This section describes the timing parameters associated with the block RAM in Virtex-5 devices (illustrated in Figure 4-14). The switching characteristics section in the Virtex-5 FPGA Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software are also available for reference. www.xilinx.com Virtex-5 FPGA User Guide...

  • Page 135: Block Ram Timing Parameters

    Block RAM Timing Model Block RAM Timing Parameters Table 4-11 shows the Virtex-5 FPGA block RAM timing parameters. Table 4-11: Block RAM Timing Parameters Control Parameter Function Description Signal Setup and Hold Relative to Clock (CLK) = Setup time (before clock edge) and T...

  • Page 136: Block Ram Timing Characteristics

    Whenever EN is asserted, all address changes must meet the specified setup and hold window. Asynchronous address changes can affect the memory content and block RAM functionality in an unpredictable way. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 137: Clock Event 2

    5, the enable signal becomes invalid (Low) at the RCCK_EN EN input of the block RAM. • After clock event 5, the data on the DO outputs of the block RAM is unchanged. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 138: Block Ram Timing Model

    + NET] + T IOPI RCCK_SSR Synchronous + [NET + T RCKO_DO IOOP Set/Reset Data + NET] BCCKO_O BUFGCTRL Clock + NET] IOPI ug190_4_14_022207 Figure 4-15: Block RAM Timing Model www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 139: Block Ram Retargeting

    Block RAM Retargeting Block RAM Retargeting Table 4-12 suggests the most appropriate primitives to choose when mapping a Virtex-4 FPGA block RAM design in a new Virtex-5 FPGA design. Table 4-12: Block RAM Retargeting Virtex-4 Block RAM 18k Virtex-5 Block RAM...

  • Page 140: Synchronous Fifo

    Virtex-4 FPGA designs used the same FIFO logic for multirate and synchronous FIFOs, thus flag latency in synchronous FIFOs can vary. By setting the EN_SYN attribute to TRUE when using Virtex-5 FPGA synchronous FIFOs, any clock cycle latency when asserting or deasserting flags is eliminated.

  • Page 141: Synchronous Fifo Implementations

    EN_SYN = TRUE = 1.9ns DO_REG = 0 EN_SYN = TRUE DO_REG = 1 EN_SYN = FALSE DO_REG = 1 ug190_c4_x1_071007 Figure 4-16: Synchronous FIFO Data Timing Diagram Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 142: Fifo Architecture: A Top-Level View

    FIFO36 primitive. X-Ref Target - Figure 4-18 FIFO36 DI[31:0] DO[31:0] DIP[3:0] DOP[3:0] RDEN WRCOUNT[12:0] RDCLK RDCOUNT[12:0] FULL WREN EMPTY WRCLK ALMOSTFULL ALMOSTEMPTY RDERR WRERR ug190_4_15_021107 Figure 4-18: FIFO36 Primitive www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 143: Fifo Port Descriptions

    Synchronous to WRCLK. The offset for this flag is user configurable. See Table 4-16 for the clock latency for flag deassertion. EMPTY Output FIFO is empty. No additional reads are accepted. Synchronous to RDCLK. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 144: Fifo Operations

    After the first word is written into an empty FIFO, this word automatically appears at DO before RDEN is asserted. Subsequent Read operations require Empty to be Low and RDEN to be High. Figure 4-20 illustrates the difference between standard mode and FWFT mode. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 145: Status Flags

    RDCLK. The empty condition can only be terminated by WRCLK, usually asynchronous to RDCLK. The falling edge of EMPTY must, therefore, artificially be moved onto the RDCLK time domain. Since the two clocks have an unknown phase Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 146: Almost Empty Flag

    FIFO queue. When the FIFO is full, the write pointer will be frozen. The Virtex-5 FPGA Full flag is deasserted three write clock cycles after two subsequent read operations. In Virtex-4 FPGA designs a Full flag is asserted one write clock cycle after the last write, and is deasserted three write clock cycle after the first read.

  • Page 147: Fifo Attributes

    2. If a FIFO18 is constrained to FIFO18_X#Y#, corresponding to the lower RAMB18_X#Y# of the RAMB18 pair, a RAMB18 can be constrained to the upper RAMB18_X#Y# of the pair. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 148: Fifo Almost Full/Empty Flag Offset Range

    FIFO is about to reach its limits. Since the full capacity of any FIFO is normally not critical, most applications use the ALMOST_FULL flag not only as a warning but also as a signal to stop writing. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 149: Fifo Vhdl And Verilog Templates

    RDERR outputs of the FIFO. Clock to write error WRERR Time after WRCLK that the Write Error signal is stable RCKO_WRERR output at the WRERR outputs of the FIFO. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 150: Fifo Timing Characteristics

    (T RCDCK_DI RCDCK_DIP 5. In the Virtex-5 FPGA Data Sheet, WRITE and READ enables are combined into T RCCK_EN FIFO Timing Characteristics The various timing parameters in the FIFO are described in this section. There is also additional data on FIFO functionality.

  • Page 151: Case 1: Writing To An Empty Fifo

    EMPTY is deasserted one read-clock earlier than clock event 3. If the rising WRCLK edge is close to the rising RDCLK edge, EMPTY could be deasserted one RDCLK period later. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 152: Case 2: Writing To A Full Or Almost Full Fifo

    X-Ref Target - Figure 4-22 WRCLK FCCK_WREN FCCK_WREN WREN FDCK_DI FDCK_DI FDCK_DI RDCLK RDEN FCKO_FULL FULL AFULL FCKO_WERR FCKO_WERR FCKO_AFULL WRERR ug190_4_18_012605 Figure 4-22: Writing to a Full / Almost Full FIFO www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 153 WRERR output pin of the FIFO. The write error signal is asserted/deasserted at every write-clock positive edge. As long as both the write enable and Full signals are true, write error will remain asserted. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 154: Case 3: Reading From A Full Fifo

    Read enable remains asserted at the RDEN input of the FIFO. • At time T , after clock event 5 (RDCLK), Almost FULL is deasserted at the FCKO_AFULL AFULL pin. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 155: Case 4: Reading From An Empty Or Almost Empty Fifo

    , after clock event 2 (RDCLK), Empty is asserted at the EMPTY FCKO_EMPTY output pin of the FIFO. In the event that the FIFO is empty and a write followed by a read is performed, the EMPTY signal remains asserted. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 156: Case 5: Resetting All Flags

    Reset is an asynchronous signal used to reset all flags. Hold the reset signal High for three read and write clock cycles to ensure that all internal states and flags are reset to the correct value. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 157: Case 6: Simultaneous Read And Write For Multirate Fifo

    When using a single clock for RDCLK and WRCLK, use the FIFO in synchronous mode (EN_SYN=TRUE). FIFO Applications A FIFO larger than a single Virtex-5 FPGA FIFO block can be created by: • Cascading two or more FIFOs to form a deeper FIFO.

  • Page 158: Connecting Fifos In Parallel To Increase Width

    This ECC configuration option is available with a 36K block RAM simple dual-port primitive (RAMB36SDP) or a 36K FIFO primitive (FIFO36_72). A Virtex-4 FPGA ECC 18K block RAM mapped for a Virtex-5 FPGA design will occupy the entire RAMB36 site. FIFO36_72 supports standard ECC mode only.

  • Page 159: Ecc Modes Overview

    • The NO_CHANGE or WRITE_FIRST modes of the normal block RAM operation are not applicable to the ECC configuration. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 160: Top-Level View Of The Block Ram Ecc Architecture

    Chapter 4: Block RAM Top-Level View of the Block RAM ECC Architecture Figure 4-28 shows the top-level view of a Virtex-5 FPGA block RAM in ECC mode. X-Ref Target - Figure 4-28 wraddr WRADDR[8:0] rdaddr RDADDR[8:0] DIP[7:0] ECCPARITY[7:0] 64-bit EN_ECC_WRITE...

  • Page 161: Block Ram And Fifo Ecc Primitive

    X-Ref Target - Figure 4-30 FIFO36_72 DI[63:0] DO[63:0] DOP[7:0] DIP[7:0] ECCPARITY[7:0] SBITERR DBITERR FULL WREN EMPTY RDEN ALMOSTFULL ALMOSTEMPTY WRCLK WRERR RDCLK RDERR WRCOUNT[8:0] RDCOUNT[8:0] ug190_4_34_022207 Figure 4-30: FIFO36_72: FIFO ECC Primitive Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 162: Block Ram And Fifo Ecc Port Descriptions

    1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and DBITERR indicate these three conditions. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 163 1. Hamming code implemented in the FIFO ECC logic detects one of three conditions: no detectable error, single-bit error detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and DBITERR indicate these three conditions. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 164: Block Ram And Fifo Ecc Attributes

    Must be set using hexadecimal notation. FIRST_WORD_FALL_THROUGH When set to TRUE, the first word written into the empty FIFO36_72 appears at the Boolean TRUE, FALSE FALSE FIFO36_72 output without RDEN asserted. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 165: Ecc Modes Of Operation

    TRCKO_DO (Register Mode) DOP[7:0] (Register Mode) Single Bit Error SBITERR (Register Mode) TRCKO_ECC_SBITERR (Register Mode) Double Bit Error DBITERR (Register Mode) TRCKO_ECC_DBITERR (Register Mode) ug190_4_33_020707 Figure 4-32: ECC Read Operation Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 166: Standard Ecc

    ECC parity PA (hex) are generated internally, appended to the 64 data bits, and written into the memory. Immediately after the write, the parity value PA appears at output ECCPARITY[7:0]. Since ECC parity is generated internally, DIP[7:0] pins are not used. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 167: Ecc Decode-Only

    The ECC decoder also detects when double-bit error in parity bits occurs, and when a single-bit error in the data bits and a single-bit error in the corresponding parity bits occurs. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 168: Ecc Timing Characteristics

    A. ♦ At time TRCKO_ECCR_DBITERR (register mode), after time T3R, DBITERR is asserted if double-bit error is detected on data set B. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 169: Encode-Only Ecc Write Timing

    Decode-only ECC read timing is the same as standard ECC read timing. Block RAM ECC Mode Timing Parameters Table 4-25 shows the Virtex-5 FPGA block RAM ECC mode timing parameters. Table 4-25: Block RAM ECC Mode Timing Parameters Control Parameter...

  • Page 170: Creating A Deliberate Error In A 72-Bit Word

    RCKO_ECC Data Sheet. 4. T and T are combined into the T parameter in the Virtex-5 FPGA Data Sheet. RCKO_ECC_SBITERR RCKO_ECC_DBITERR RCKO_ECCR Creating a Deliberate Error in a 72-bit Word To deliberately create an error in a 72-bit word, configure the ECC decode-only mode and create a 72-bit word with one or two bit errors.

  • Page 171: Block Ram Ecc Vhdl And Verilog Templates

    RAMB36 primitive. When placing block RAM and FIFO primitives in the same location, the FIFO must occupy the lower port. X-Ref Target - Figure 4-33 RAMB18 RAMB18SDP RAMB18 RAMB18SDP RAMB18 RAMB18SDP FIFO18 FIFO18_36 ug0190_4_35_050208 Figure 4-33: Legal Block RAM and FIFO Combinations Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 172 Chapter 4: Block RAM www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 173: Chapter 5: Configurable Logic Blocks (Clbs)

    Figure 5-1: Arrangement of Slices within the CLB The Xilinx tools designate slices with the following definitions. An “X” followed by a number identifies the position of each slice in a pair as well as the column position of the slice.

  • Page 174: Slice Description

    Slices that support these additional functions are called SLICEM; others are called SLICEL. SLICEM (shown in Figure 5-3) represents a superset of elements and connections found in all slices. SLICEL is shown in Figure 5-4. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 175 LATCH INIT1 INIT0 SRHIGH MC31 SRLOW WA1-WA6 SR REV AMUX DPRAM64/32 SPRAM64/32 SRL32 SRL16 LATCH INIT1 INIT0 SRHIGH MC31 SRLOW WA1-WA6 SR REV WSGEN UG190_c5_03_022709 Figure 5-3: Diagram of SLICEM Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 176 Each CLB can contain zero or one SLICEM. Every other CLB column contains a SLICEMs. In addition, the two CLB columns to the left of the DSP48E columns both contain a SLICEL and a SLICEM. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 177: Clb/Slice Configurations

    Shift Registers Carry Chains 256 bits 128 bits Notes: 1. SLICEM only, SLICEL does not have distributed RAM or shift registers. Table 5-2: Virtex-5 FPGA Logic Resources Available in All CLBs CLB Array Number of Maximum Shift Number of Device...

  • Page 178: Look-Up Table (Lut)

    Table 5-4 provide truth tables for SR and REV depending on whether SRLOW or SRHIGH is used. Table 5-3: Truth Table when SRLOW is Used (Default Condition) Function No Logic Change www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 179 SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set individually for each storage element in a slice. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 180: Distributed Ram And Memory (Available In Slicem Only)

    For a write operation, the Write Enable (WE) input, driven by either the CE or WE pin of a SLICEM, must be set High. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 181 Figure 5-14 illustrate various example distributed RAM configurations occupying one SLICEM. When using x2 configuration (RAM32X2Q), A6 and WA6 are driven High by the software to keep O5 and O6 independent. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 182 DOD[1] WCLK (WE) DPRAM32 DOC[0] C[5:1] ADDRC[4:0] A[6:1] WA[6:1] DOC[1] DPRAM32 DOB[0] B[5:1] ADDRB[4:0] A[6:1] WA[6:1] DOB[1] DPRAM32 DOA[0] A[5:1] ADDRA[4:0] A[6:1] WA[6:1] DOA[1] UG190_5_06_032706 Figure 5-6: Distributed RAM (RAM32X2Q) www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 183 C[5:1] RADDR[5:1] A[6:1] RADDR[6] = 1 WA[6:1] O[2] DPRAM32 DATA[3] O[3] DATA[4] B[5:1] A[6:1] WA[6:1] O[4] DPRAM32 DATA[5] O[5] DATA[6] A[5:1] A[6:1] WA[6:1] O[6] UG190_5_06_032706 Figure 5-7: Distributed RAM (RAM32X6SDP) Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 184 If two dual-port 64 x 1-bit modules are built, the two RAM64X1D primitives can occupy a SLICEM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 64 x 2-bit dual-port distributed RAM. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 185 DPRAM64 (C[6:1]) ADDRC A[6:1] Registered Output WA[6:1] (Optional) DPRAM64 (B[6:1]) Registered ADDRB A[6:1] Output WA[6:1] (Optional) DPRAM64 (A[6:1]) Registered ADDRA A[6:1] Output WA[6:1] (Optional) ug190_5_10_032706 Figure 5-10: Distributed RAM (RAM64X1Q) Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 186 O[3] A[6:1] A[6:1] WA[6:1] UG190_5_06_050506 Figure 5-11: Distributed RAM (RAM64X3SDP) Implementation of distributed RAM configurations with depth greater than 64 requires the usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX). www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 187 SLICEM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 128 x 2-bit single-port distributed RAM. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 188 A[6:0] A[6:1] WA[7:1] (CLK) WCLK (WE) Registered DPRAM64 F7BMUX Output (Optional) A[6:1] WA[7:1] DPRAM64 DPRA[6:0] A[6:1] WA[7:1] Registered DPRAM64 F7AMUX Output (Optional) A[6:1] WA[7:1] UG190_5_13_050506 Figure 5-13: Distributed RAM (RAM128X1D) www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 189 Distributed RAM configurations greater than the provided examples require more than one SLICEM. There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between slices. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 190: Read Only Memory (Rom)

    LUT is unused and the software automatically ties it to a logic High. The configurable shift registers cannot be set or reset. The read is asynchronous; however, a storage element www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 191 X-Ref Target - Figure 5-16 32-bit Shift Register SHIFTIN (D) SHIFTOUT(Q31) Address (A[4:0]) UG190_5_16_050506 Figure 5-16: Representation of a Shift Register Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 192 SRL32 SHIFTIN (D) A[5:0] A[6:2] A5 (AX) MC31 (CLK) (WE/CE) Output (Q) (AQ) Registered SRL32 F7AMUX Output (Optional) (MC31) A[6:2] MC31 SHIFTOUT (Q63) UG190_5_18_050506 Figure 5-18: 64-bit Shift Register Configuration www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 193 MC31 BX (A6) (CLK) (WE/CE) (BMUX) Output (Q) (BQ) Registered F8MUX Output (Optional) SRL32 A[6:2] MC31 AX (A5) SRL32 Not Used F7AMUX A[6:2] UG190_c5_19_020909 Figure 5-19: 96-bit Shift Register Configuration Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 194 The Q output is determined by the 5-bit address. Each time a new address is applied to the 5-input address pins, the new bit position value is available on the Q output after the time www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 195: Multiplexers

    These wide input multiplexers are implemented in one level or logic (or LUT) using the dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow LUT combinations of up to four LUTs in a slice. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 196: Designing Large Multiplexers

    A[6:1] Output Input (Optional) 4:1 MUX Output (A[6:1]) (AQ) Registered SEL A [1:0], DATA A [3:0] A[6:1] Output Input (CLK) (Optional) UG190_5_21_050506 Figure 5-21: Four 4:1 Multiplexers in a Slice www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 197 (AMUX) 8:1 MUX Output (2) (AQ) Registered Output (A[6:1]) SEL A [1:0], DATA A [3:0] A[6:1] Input (2) (Optional) (AX) SELF7(2) UG190_5_22_090806 Figure 5-22: Two 8:1 Multiplexers in a Slice Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 198: Fast Lookahead Carry Logic

    However, there are no direct connections between slices to form these wide multiplexers. Fast Lookahead Carry Logic In addition to function generators, dedicated carry logic is provided to perform fast arithmetic addition and subtraction in a slice. A Virtex-5 FPGA CLB has two separate carry chains, as shown in Figure 5-1.
  • Page 199 O5 output of a function generator or the BYPASS input (AX, BX, CX, or DX) of a slice. The former input is used to create a multiplier, while the latter is used Virtex-5 FPGA User Guide www.xilinx.com...

  • Page 200: Clb / Slice Timing Models

    Most of the timing parameters found in the section on switching characteristics are described in this chapter. All timing parameters reported in the Virtex-5 FPGA Data Sheet are associated with slices and CLBs. The following sections correspond to specific switching characteristics sections in the Virtex-5 FPGA Data Sheet: •...

  • Page 201: General Slice Timing Model And Parameters

    CLB / Slice Timing Models General Slice Timing Model and Parameters A simplified Virtex-5 FPGA slice is shown in Figure 5-25. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown.

  • Page 202: Timing Parameters

    Notes: 1. This parameter includes a LUT configured as two five-input functions. 2. T = Setup Time (before clock edge), and T = Hold Time (after clock edge). XXCK CKXX www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 203: Timing Characteristics

    CLB / Slice Timing Models Timing Characteristics Figure 5-26 illustrates the general timing characteristics of a Virtex-5 FPGA slice. X-Ref Target - Figure 5-26 DICK AX/BX/CX/DX (DATA) SRCK SR (RESET) AQ/BQ/CQ/DQ (OUT) ug190_5_26_050506 Figure 5-26: General Slice Timing Characteristics •...
  • Page 204 Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only) Figure 5-27 illustrates the details of distributed RAM implemented in a Virtex-5 FPGA slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown.

  • Page 205: Distributed Ram Timing Parameters

    1. This parameters includes a LUT configured as a two-bit distributed RAM. 2. T = Setup Time (before clock edge), and T = Hold Time (after clock edge). XXCK CKXX 3. Parameter includes AI/BI/CI/DI configured as a data input (DI2). Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 206: Distributed Ram Timing Characteristics

    Chapter 5: Configurable Logic Blocks (CLBs) Distributed RAM Timing Characteristics The timing characteristics of a 16-bit distributed RAM implemented in a Virtex-5 FPGA slice (LUT configured as RAM) are shown in Figure 5-28. X-Ref Target - Figure 5-28 A/B/C/D (ADDR)

  • Page 207: Slice Srl Timing Model And Parameters (Available In Slicem Only)

    Slice SRL Timing Model and Parameters (Available in SLICEM only) Figure 5-29 illustrates shift register implementation in a Virtex-5 FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown.

  • Page 208: Slice Srl Timing Parameters

    3. Parameter includes AI/BI/CI/DI configured as a data input (DI2) or two bits with a common shift. Slice SRL Timing Characteristics Figure 5-30 illustrates the timing characteristics of a 16-bit shift register implemented in a Virtex-5 FPGA slice (a LUT configured as an SRL). X-Ref Target - Figure 5-30 Write Enable (WE)
  • Page 209 DMUX output of the slice via the MC31 output of LUT A (SRL). This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T after clock event 1. WOSCO Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 210: Slice Carry-Chain Timing Model And Parameters

    Slice Carry-Chain Timing Model and Parameters Figure 5-24, page 199 illustrates a carry chain in a Virtex-5 FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown.

  • Page 211: Clb Primitives

    The input and output data are 1-bit wide (with the exception of the 32-bit RAM). Figure 5-32 shows generic single-port, dual-port, and quad-port distributed RAM primitives. The A, ADDR, and DPRA signals are address buses. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 212: Port Signals

    Following an active write clock edge, the data out (O, SPO, or DOD[#:0]) reflects the newly written data. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 213: Shift Registers (Srls) Primitive

    The address input selects the bit (range 0 to 31) to be read. The nth bit is available on the output pin (Q). Address inputs have no effect on the cascadable output pin (Q31). It is always the last bit of the shift register (bit 31). Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 214: Other Shift Register Applications

    0b00111. Alternatively, shift register length can be limited to 71 bits (address tied to 0b00110) and a flip-flop can be used as the last register. (In an SRLC32E primitive, the shift register length is the address input + 1). www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 215: Multiplexer Primitives

    This primitive works in conjunction with LUTs in order to build adders and multipliers. This primitive is generally inferred by synthesis tools from standard RTL code. The synthesis tool can identify the arithmetic and/or logic functionality that best maps to this Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 216: Port Signals

    The carry in input is used to cascade slices to form longer carry chain. To create a longer carry chain, the CO[3] output of another CARRY4 is simply connected to this pin. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 217: Chapter 6: Selectio Resources

    Chapter 8, “Advanced SelectIO Logic Resources,” describes the data serializer/deserializer (SERDES). An I/O tile contains two IOBs, two ILOGICs, two OLOGICs, and two IODELAYs. Figure 6-1 shows a Virtex-5 FPGA I/O tile. X-Ref Target - Figure 6-1 IODELAY (Chapter 7) ILOGIC...

  • Page 218: Selectio Resources Introduction

    • Differential and V dependent inputs are powered by V CCAUX Each Virtex-5 FPGA I/O tile contains two IOBs, and also two ILOGIC blocks and two OLOGIC blocks, as described in Chapter 7, “SelectIO Logic Resources.” Figure 6-2 shows the basic IOB and its connections to the internal logic and the device Pad.

  • Page 219: Reference Voltage

    BANK BANK 20 I/O 40 I/O 40 I/O ug190_6_03_021306 Figure 6-3: Virtex-5 FPGA XC5VLX30 I/O Banks Reference Voltage (V ) Pins Low-voltage, single-ended I/O standards with a differential amplifier input buffer require an input reference voltage (V ). V is an external input into Virtex-5 devices. Within...

  • Page 220: Virtex-5 Fpga Digitally Controlled Impedance (Dci)

    UG190_6_95_019507 Figure 6-4: DCI Use within a Bank The Virtex-5 FPGA banks using DCI I/O standards now have the option of deriving the DCI impedance values from another DCI bank. With DCI cascading, one bank (the master bank) must have its VRN/VRP pins connected to external reference resistors. Also, at least one I/O in that bank (the master bank) must be configured as DCI.
  • Page 221 6, and bank 3 cannot be cascaded with bank 5. Bank 3 can only be cascaded with bank 1, and bank 4 can only be cascaded with bank 2. Figure 6-5 shows DCI cascading support over multiple banks. Bank B is the master bank. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 222 DCI I/O standard compatibility is not constrained to one bank when DCI cascading is implemented; it extends across all master and slave banks. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 223: Xilinx Dci

    The coarse impedance calibration during the first phase of impedance adjustment can be invoked after configuration by instantiating the DCIRESET primitive. By toggling the RST input to the DCIRESET primitive while the device is operating, the DCI state machine is Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 224: Controlled Impedance Driver (Source Termination)

    LVDCI_18, LVDCI_25, LVDCI_33, HSLVDCI_15, HSLVDCI_18, HSLVDCI_25, and HSLVDCI_33. Figure 6-6 illustrates a controlled impedance driver in a Virtex-5 device. X-Ref Target - Figure 6-6 Virtex-5 DCI UG190_6_04_012706 Figure 6-6: Controlled Impedance Driver www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 225: Controlled Impedance Driver With Half Impedance (Source Termination)

    Both GTL and HSTL standards are controlled by 50 Ω reference resistors. The DCI I/O standards supporting single termination are: GTL_DCI, GTLP_DCI, HSTL_III_DCI, HSTL_III_DCI_18, HSTL_IV_DCI, and HSTL_IV_DCI_18. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 226: Input Termination To Vcco/2 (Split Termination)

    Table 6-1. Table 6-1: DCI Input Standards Supporting Split Termination HSTL_I_DCI DIFF_HSTL_I_DCI SSTL2_I_DCI DIFF_SSTL2_I_DCI HSTL_I_DCI_18 DIFF_HSTL_I_DCI_18 SSTL2_II_DCI DIFF_SSTL2_II_DCI HSTL_II_DCI DIFF_HSTL_II_DCI SSTL18_I_DCI DIFF_SSTL18_I_DCI HSTL_II_DCI_18 DIFF_HSTL_II_DCI_18 SSTL18_II_DCI DIFF_SSTL18_II_DCI HSTL_II_T_DCI SSTL2_II_T_DCI HSTL_II_T_DCI_18 SSTL18_II_T_DCI www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 227: Driver With Termination To Vcco (Single Termination)

    Both GTL and HSTL standards need 50 Ω external reference resistors. The DCI I/O standards supporting drivers with single termination are: GTL_DCI, GTLP_DCI, HSTL_IV_DCI, and HSTL_IV_DCI_18. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 228 50 Ω external reference resistors. The DCI output standards supporting drivers with split termination are shown in Table 6-2. Table 6-2: DCI Output Standards Supporting Split Termination HSTL_II_DCI DIFF_HSTL_II_DCI SSTL2_II_DCI DIFF_SSTL2_II_DCI HSTL_II_DCI_18 DIFF_HSTL_II_DCI_18 SSTL18_II_DCI DIFF_SSTL18_II_DCI www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 229: Dci In Virtex-5 Device I/O Standards

    (VRN and VRP) in the bank. Where this is required, these two multipurpose pins cannot be used as general-purpose I/O. Refer to the Virtex-5 FPGA pinout tables for the specific pin locations. Pin VRN must be pulled up to V by its reference resistor.

  • Page 230: Dci Usage Examples

    Figure 6-16 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. • Figure 6-17 provides examples illustrating the use of the SSTL2_I_DCI and SSTL2_II_DCI I/O standards. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 231 VRN = VRP = R = Z 0 Resistor 50Ω 50Ω 50Ω 50Ω Recommended Notes: ug190_6_14_021206 1. Z 0 is the recommended PCB trace impedance. Figure 6-16: HSTL DCI Usage Examples Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 232 1. The SSTL-compatible 25 Ω or 20 Ω series resistor is accounted for in the DCI buffer, and it is not DCI controlled. 2. Z 0 is the recommended PCB trace impedance. ug190_6_15_041106 Figure 6-17: SSTL DCI Usage Examples www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 233: Virtex-5 Fpga Selectio Primitives

    Figure 6-18: Input Buffer (IBUF/IBUFG) Primitives The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at clock input sites.

  • Page 234: Obuft

    Figure 6-22 shows the differential input buffer primitive X-Ref Target - Figure 6-22 IBUFDS/IBUFGDS Output to FPGA – Inputs from device pads ug190_6_20_022806 Figure 6-22: Differential Input Buffer Primitive (IBUFDS/IBUFGDS) www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 235: Ibufds_Diff_Out

    Virtex-5 FPGA SelectIO Primitives IBUFDS_DIFF_OUT Figure 6-23 shows the differential input buffer primitive with a complementary output (OB). This primitive is for expert users only. X-Ref Target - Figure 6-23 IBUFDS_DIFF_OUT Output Input into FPGA from Device Pad UG190_6_97_122208 Figure 6-23: Differential Input Buffer Primitive (IBUFDS_DIFF_OUT)

  • Page 236: Iobufds

    Figure 6-26: Differential Input/Output Buffer Primitive (IOBUFDS) Virtex-5 FPGA SelectIO Attributes/Constraints Access to some Virtex-5 FPGA I/O resource features (e.g., location constraints, input delay, output drive strength, and slew rate) is available through the attributes/constraints associated with these features. For more information a Constraints Guide is available on the Xilinx website with syntax examples and VHDL/Verilog reference code.

  • Page 237: Output Slew Rate Attributes

    PULLDOWN • KEEPER Differential Termination Attribute The differential termination (DIFF_TERM) attribute is designed for the Virtex-5 FPGA supported differential input I/O standards. It is used to turn the built-in, 100Ω, differential termination on or off. Virtex-5 FPGA User Guide www.xilinx.com...

  • Page 238: Virtex-5 Fpga I/O Resource Vhdl/Verilog Examples

    To specify the DIFF_TERM attribute, set the appropriate value in the generic map (VHDL) or inline parameter (Verilog) of the instantiated IBUFDS or IBUGDS component. Please refer to the ISE Language Templates or the Virtex-5 FPGA HDL Libraries Guide for the proper syntax for instantiating this component and setting the DIFF_TERM attribute.

  • Page 239: Specific Guidelines For I/O Supported Standards

    The following subsections provide an overview of the I/O standards supported by all Virtex-5 devices. While most Virtex-5 FPGA I/O supported standards specify a range of allowed voltages, this chapter records typical voltage values only. Detailed information on each specification can be found on the Electronic Industry Alliance JEDEC web site at http://www.jedec.org.
  • Page 240 (mA) Note 2 – Notes: 1. V and V for lower drive currents are sample tested. 2. Supported DRIVE strengths are 2, 4, 6, 8, 12, 16, and 24 mA www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 241: Lvcmos (Low Voltage Complementary Metal Oxide Semiconductor)

    R S = Z 0 – R D LVCMOS LVCMOS R P = Z 0 Note: V is any voltage from 0V to V CCO ug190_6_26_022806 Figure 6-29: LVCMOS Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 242 IBUF/IBUFG OBUF/OBUFT IOBUF IOSTANDARD LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS15 LVCMOS15 LVCMOS15 DRIVE UNUSED 2, 4, 6, 8, 12, 16 2, 4, 6, 8, 12, 16 SLEW UNUSED {FAST, SLOW} {FAST, SLOW} www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 243: Lvdci (Low Voltage Digitally Controlled Impedance)

    R 0 = R VRN = R VRP = Z 0 R 0 = R VRN = R VRP = Z 0 ug190_6_29_022806 Figure 6-32: Controlled Impedance Driver with Bidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 244: Lvdci_Dv2

    There are no drive strength settings for LVDCI drivers. When the driver impedance is one- half of the VRN/VRP reference resistors, it is indicated by the addition of DV2 to the attribute name. Table 6-9 lists the LVCMOS, LVDCI, and LVDCI_DV2 voltage specifications. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 245 – Notes: 1. V and V for lower drive currents are sample tested. 2. Only LVCMOS is supported at + 1.2V with valid DRIVE attributes of 2, 4, 6, 8. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 246: Hslvdci (High-Speed Low Voltage Digitally Controlled Impedance)

    1.5V, 1.8V, 2.5V, and 3.3V. Select V to provide the optimum noise margin in specific use conditions. Table 6-10: HSLVDCI Input DC Voltage Specifications Standard – – + 0.1 – – – – – 0.1 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 247: Pci-X, Pci-33, Pci-66 (Peripheral Component Interconnect)

    V (mA) (Note 1) – – at V (mA) (Note 1) – – Notes: 1. Tested according to the relevant specification. 2. For complete specifications, refer to the PCI-X specification. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 248: Gtl (Gunning Transceiver Logic)

    GTL (Gunning Transceiver Logic) The Gunning Transceiver Logic (GTL) standard is a high-speed bus standard (JESD8.3) invented by Xerox. Xilinx has implemented the terminated variation for this standard. This standard requires a differential amplifier input buffer and an open-drain output buffer.

  • Page 249: Gtlp (Gunning Transceiver Logic Plus)

    X-Ref Target - Figure 6-39 = 1.5V = 1.5V R VRP = Z 0 = 50Ω 50Ω Z 0 = 50 – = 1.0V ug190_6_37_030206 Figure 6-39: GTLP_DCI Internal Parallel Driver and Receiver Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 250: Hstl (High-Speed Transceiver Logic)

    To support clocking high-speed memory interfaces, a differential version of this standard was added. Virtex-5 FPGA I/O supports all four classes for 1.5V and 1.8V and the differential versions of classes I and II. These differential versions of the standard require a differential amplifier input buffer and a push-pull output buffer.

  • Page 251: Hstl_ Ii_Dci, Hstl_ Iv_Dci, Hstl_ Ii_Dci_18, Hstl_ Iv_Dci_18

    Differential HSTL class I pairs complimentary single-ended HSTL_I type drivers with a differential receiver, including on-chip differential split-thevenin termination. Differential HSTL class I is intended to be used in unidirectional links. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 252: Hstl Class I

    2. Per EIA/JESD8-6, “The value of V is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.” www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 253: Differential Hstl Class I

    = 2Z 0 = 100Ω DIFF_HSTL_I_DCI = 1.5V – DIFF_HSTL_I_DCI = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug190_6_40_030206 Figure 6-42: Differential HSTL (1.5V) Class I DCI Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 254: Hstl Class Ii

    = 2Z 0 = 100Ω = 2Z 0 = 100Ω HSTL_II_DCI HSTL_II_DCI – = 0.75V = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug190_6_41_030206 Figure 6-43: HSTL (1.5V) Class II Unidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 255 = 2Z 0 = 100Ω HSTL_II_DCI HSTL_II_DCI – = 0.75V = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 0.75V ug190_6_42_030306 Figure 6-44: HSTL (1.5V) Class II Bidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 256: Differential Hstl Class Ii

    X-Ref Target - Figure 6-45 External Termination = 0.75V = 0.75V DIFF_HSTL_II 50Ω 50Ω DIFF_HSTL_II – = 0.75V = 0.75V DIFF_HSTL_II 50Ω 50Ω ug190_6_40_030206 Figure 6-45: Differential HSTL (1.5V) Class II Unidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 257 = 0.75V = 0.75V DIFF_HSTL_II DIFF_HSTL_II 50Ω 50Ω = 0.75V = 0.75V DIFF_HSTL_II DIFF_HSTL_II 50Ω 50Ω DIFF_HSTL_II DIFF_HSTL_II – – ug190_6_45_020306 Figure 6-47: Differential HSTL (1.5V) Class II Bidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 258 + 0.60 DIFF (Crossover) 0.68 – 0.90 Notes: 1. Common mode voltage: V – ((V – V )/2) 2. Crossover point: V where V – V = 0 (AC coupled) www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 259: Hstl Class Iii

    2. Per EIA/JESD8-6, “The value of V is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.” Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 260: Hstl Class Iv

    – = 0.9V = 1.5V = 1.5V = Z 0 = 50Ω = Z 0 = 50Ω HSTL_IV_DCI HSTL_IV_DCI – = 0.9V ug190_6_48_030306 Figure 6-50: HSTL Class IV Unidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 261 = 0.9V = 1.5V = 1.5V = Z 0 = 50Ω = Z 0 = 50Ω HSTL_IV_DCI HSTL_IV_DCI – = 0.9V = 0.9V ug190_6_49_030306 Figure 6-51: HSTL Class IV Bidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 262: Hstl_Ii_T_Dci (1.5V) Split-Thevenin Termination

    X-Ref Target - Figure 6-52 Not 3-stated 3-stated = 1.5V = 2Z 0 = 100Ω HSTL_II_T_DCI HSTL_II_T_DCI – = 0.75V = 2Z 0 = 100Ω = 0.75V ug190_6_90_041206 Figure 6-52: HSTL_II_T_DCI (1.5V) Split-Thevenin Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 263: Hstl Class I (1.8V)

    2. Per EIA/JESD8-6, “The value of V is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.” Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 264: Differential Hstl Class I (1.8V)

    = 2Z 0 = 100Ω DIFF_HSTL_I_DCI_18 = 1.8V – DIFF_HSTL_I_DCI_18 = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug190_6_52_030306 Figure 6-55: Differential HSTL (1.8V) Class I DCI Unidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 265: Hstl Class Ii (1.8V)

    = 2Z 0 = 100Ω HSTL_II_DCI_18 HSTL_II_DCI_18 – = 0.9V = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug190_6_53_030306 Figure 6-56: HSTL Class II (1.8V) with Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 266 = 2Z 0 = 100Ω HSTL_II_DCI_18 HSTL_II_DCI_18 – = 0.9V = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 0.9V ug190_6_54_030306 Figure 6-57: HSTL Class II (1.8V) with Bidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 267: Differential Hstl Class Ii (1.8V)

    X-Ref Target - Figure 6-58 External Termination = 0.9V = 0.9V DIFF_HSTL_II_18 50Ω 50Ω DIFF_HSTL_II_18 = 0.9V = 0.9V – DIFF_HSTL_II_18 50Ω 50Ω ug190_6_55_030306 Figure 6-58: Differential HSTL (1.8V) Class II Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 268 = 0.9V = 0.9V DIFF_HSTL_II_18 DIFF_HSTL_II_18 50Ω 50Ω = 0.9V = 0.9V DIFF_HSTL_II_18 DIFF_HSTL_II_18 50Ω 50Ω DIFF_HSTL_II_18 DIFF_HSTL_II_18 – – ug190_6_57_030306 Figure 6-60: Differential HSTL (1.8V) Class II Bidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 269 + 0.60 DIFF (Crossover) 0.83 – 1.08 Notes: 1. Common mode voltage: V – ((V – V )/2) 2. Crossover point: V where V – V = 0 (AC coupled) Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 270: Hstl Class Iii (1.8V)

    2. Per EIA/JESD8-6, “The value of V is to be selected by the user to provide optimum noise margin in the use conditions specified by the user.” www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 271: Hstl Class Iv (1.8V)

    – = 1.1V ug190_6_60_030306 Figure 6-63: HSTL Class IV (1.8V) with Unidirectional Termination Figure 6-64 shows a sample circuit illustrating a valid bidirectional termination technique for HSTL Class IV (1.8V). Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 272 = 1.8V = 1.8V = Z 0 = 50Ω = Z 0 = 50Ω HSTL_IV_DCI_18 HSTL_IV_DCI_18 – = 1.1V = 1.1V ug190_6_61_030306 Figure 6-64: HSTL Class IV (1.8V) with Bidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 273: Hstl_Ii_T_Dci_18 (1.8V) Split-Thevenin Termination

    X-Ref Target - Figure 6-65 Not 3-stated 3-stated = 1.8V = 2Z 0 = 100Ω HSTL_II_T_DCI_18 HSTL_II_T_DCI_18 – = 0.9V = 2Z 0 = 100Ω = 0.9V ug190_6_91_041206 Figure 6-65: HSTL_II_T_DCI_18 Split-Thevenin Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 274: Hstl Class I (1.2V)

    SSTL2 is defined by the JEDEC standard JESD8-9B and SSTL18 is defined by the JEDEC standard JESD8-15. The SSTL2 standard has two classes; Class I is for unidirectional and class II is for bidirectional signaling. Virtex-5 FPGA I/O supports both standards for single-ended signaling and differential signaling. This standard requires a differential amplifier input buffer and a push-pull output buffer.

  • Page 275: Sstl2_I, Sstl18_I

    3-stated. When not 3-stated, these two standards do not have parallel termination but when invoked they have an internal series resistor (25 Ω at 2.5V and 20 Ω at 1.8V.) Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 276: Sstl2 Class I (2.5V)

    = 1.25V = 2.5V = 2Z 0 = 100Ω SSTL2_I_DCI SSTL2_I_DCI – = 1.25V Ω R 0 = 25 = 2Z 0 = 100Ω ug190_6_63_030506 Figure 6-67: SSTL2 Class I Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 277: Differential Sstl2 Class I (2.5V)

    External Termination = 1.25V DIFF_SSTL2_I 50Ω R S = 25Ω DIFF_SSTL2_I = 1.25V – DIFF_SSTL2_I = 50Ω R S = 25Ω ug190_6_64_030506 Figure 6-68: Differential SSTL2 Class I Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 278 (DC) specifies the input differential voltage required for switching. 3. V (AC) indicates the voltage where the differential input signals must cross. 4. V (AC) indicates the voltage where the differential output signals must cross. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 279: Sstl2 Class Ii (2.5V)

    = 2Z 0 = 100Ω SSTL2_II_DCI SSTL2_II_DCI – = 1.25V Ω R 0 = 25 = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug190_6_66_030506 Figure 6-70: SSTL2 Class II with Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 280 R 0 = 25 = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 1.25V Ω R 0 = 25 ug190_6_67_030506 Figure 6-71: SSTL2 Class II with Bidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 281: Differential Sstl2 Class Ii (2.5V)

    = 1.25V DIFF_SSTL2_II 50Ω 50Ω R S = 25Ω DIFF_SSTL2_II = 1.25V = 1.25V – DIFF_SSTL2_II 50Ω 50Ω R S = 25Ω ug190_6_68_030506 Figure 6-72: Differential SSTL2 Class II Unidirectional Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 282 DIFF_SSTL2_II 50Ω 50Ω 25Ω 25Ω = 1.25V = 1.25V DIFF_SSTL2_II DIFF_SSTL2_II 50Ω 50Ω 25Ω 25Ω DIFF_SSTL2_II DIFF_SSTL2_II – – ug190_6_70_071707 Figure 6-74: Differential SSTL2 (2.5V) Class II with Bidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 283 (DC) specifies the input differential voltage required for switching. 3. V (AC) indicates the voltage where the differential input signals must cross. 4. V (AC) indicates the voltage where the differential output signals must cross. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 284: Sstl2_Ii_T_Dci (2.5V) Split-Thevenin Termination

    = 2Z 0 = 100Ω SSTL2_II_T_DCI SSTL2_II_T_DCI – = 1.25V Ω R 0 = 25 = 2Z 0 = 100Ω = 1.25V Ω R 0 = 25 ug190_6_92_041206 Figure 6-76: SSTL2_II_T_DCI (2.5V) Split-Thevenin Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 285: Sstl18 Class I (1.8V)

    = 1.8V = 2Z 0 = 100Ω SSTL18_I_DCI SSTL18_I_DCI – = 0.9V Ω R 0 = 20 = 2Z 0 = 100Ω ug190_6_72_030506 Figure 6-77: SSTL18 (1.8V) Class I Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 286: Differential Sstl Class I (1.8V)

    = 1.8V – DIFF_SSTL18_I_DCI = 2Z 0 = 100Ω = 2Z 0 = 100Ω Ω R 0 = 20 ug190_6_74_032206 Figure 6-79: Differential SSTL (1.8V) Class I Unidirectional DCI Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 287 (DC) specifies the input differential voltage required for switching. 4. V (AC) indicates the voltage where the differential input signals must cross. 5. V (AC) indicates the voltage where the differential output signals must cross. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 288: Sstl18 Class Ii (1.8V)

    = 2Z 0 = 100Ω ug190_6_75_030506 Figure 6-80: SSTL18 (1.8V) Class II Unidirectional Termination Figure 6-81 shows a sample circuit illustrating a valid bidirectional termination technique for SSTL (1.8V) Class II. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 289 Ω R 0 = 20 = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 0.9V Ω R 0 = 20 ug190_6_76_071707 Figure 6-81: SSTL (1.8V) Class II Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 290 1. N must be greater than or equal to –0.04 and less than or equal to 0.04. 2. V maximum is V +0.3. 3. V minimum does not conform to the formula. 4. Because SSTL_I_DCI uses a controlled-impedance driver, V and V are different. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 291: Differential Sstl Class Ii (1.8V)

    = 2Z 0 = 100Ω = 2Z 0 = 100Ω = 2Z 0 = 100Ω Ω R 0 = 20 ug190_6_78_030506 Figure 6-83: Differential SSTL (1.8V) Class II Unidirectional DCI Termination Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 292 = 2Z 0 = 100Ω = 2Z 0 = 100Ω – – = 2Z 0 = 100Ω = 2Z 0 = 100Ω ug190_6_80_030506 Figure 6-85: Differential SSTL (1.8V) Class II with DCI Bidirectional Termination www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 293: Sstl18_Ii_T_Dci (1.8V) Split-Thevenin Termination

    SSTL class I driver. The SSTL18_II_T_DCI standard behaves like a normal SSTL18_II I/O in a bidirectional environment but has the advantage of lower drive strength and lower power consumption due to the optimized termination circuit. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 294: Differential Termination: Diff_Term Attribute

    LVDS and Extended LVDS (Low Voltage Differential Signaling) Low Voltage Differential Signaling (LVDS) is a very popular and powerful high-speed interface in many system applications. Virtex-5 FPGA I/Os are designed to comply with the EIA/TIA electrical specifications for LVDS to make system and board design easier.

  • Page 295: Transmitter Termination

    The Virtex-5 FPGA LVDS transmitter does not require any external termination. Table 6-36 lists the allowed attributes corresponding to the Virtex-5 FPGA LVDS current-mode drivers. Virtex-5 FPGA LVDS current-mode drivers are a true current source and produce the proper (EIA/TIA compliant) LVDS signal. Receiver Termination...

  • Page 296: Hypertransport Protocol (Ht)

    The HyperTransport™ protocol (HT) also known as Lightning Data Transport (LDT), is a low-voltage standard for high-speed interfaces. Its differential signaling based interface is very similar to LVDS. Virtex-5 FPGA IOBs are equipped with HT buffers. Table 6-38 summarizes all the possible HT I/O standards and attributes supported.

  • Page 297: Differential Lvpecl (Low-Voltage Positive Emitter-Coupled Logic)

    Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic) LVPECL is a very popular and powerful high-speed interface in many system applications. Virtex-5 FPGA I/Os are designed to comply with the EIA/TIA electrical specifications for 2.5V LVPECL to make system and board design easier.

  • Page 298: Rules For Combining I/O Standards In The Same Bank

    No more than one Split Termination type (input or output) is allowed in the same bank. Incompatible example: HSTL_I_DCI input and HSTL_II_DCI input The implementation tools enforce these design rules. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 299 Rules for Combining I/O Standards in the Same Bank Table 6-39 summarizes the Virtex-5 FPGA supported I/O standards. Table 6-39: I/O Compatibility Termination Type I/O Standard Output Input Input Output Input LVTTL LVCMOS33 LVDCI_33 Series HSLVDCI_33 Series PCIX PCI33_3 PCI66_3...
  • Page 300 1.08 Single HSTL_IV_DCI_18 1.08 Single Single HSTL_I_DCI_18 Split HSTL_II_DCI_18 Split Split HSTL_II_T_DCI_18 Split DIFF_HSTL_I_DCI_18 Split DIFF_HSTL_II_DCI_18 Split Split SSTL18_I_DCI Split SSTL18_II_DCI Split Split SSTL18_II_T_DCI Split DIFF_SSTL18_I_DCI Split DIFF_SSTL18_II_DCI Split Split www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 301 3. N/R = no requirement. 4. RSDS_25 has the same DC specifications as LVDS_25. All information pertaining to LVDS_25 is applicable to RSDS_25. 5. I/O standard is selected using the IOSTANDARD attribute. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 302: 3.3V I/O Design Guidelines

    Clamp Diode ug190_6_85_030506 Figure 6-91: Virtex-5 FPGA I/O: 3-State Output Driver The clamp diodes offer protection against transient voltage beyond approximately + 0.5V and Ground – 0.5V. The voltage across the diode increases proportionally to the current going through it. Therefore the clamped level is not fixed and can vary www.xilinx.com...
  • Page 303 Figure 6-92, the OBUF_LVDCI_33 primitive is used to implement the source termination function in Virtex-5 FPGA output drivers. The pull-up resistor connected to VRN and the pull-down resistor connected to VRP determine the output impedance of all the output drivers in the same bank. The “Virtex-5 FPGA Digitally Controlled Impedance...

  • Page 304: Mixing Techniques

    In addition, changing the slew rate from fast to slow and/or reducing the current drive could significantly reduce overshoot and undershoot. The Virtex-5 FPGA PCB Designer’s Guide contains additional design information to assist PCB designers and signal integrity engineers. Regulating V at 3.0V...

  • Page 305: Simultaneous Switching Output Limits

    I/O standards. For designs in nominal PCBs mixing limited and “no limit” I/O standards, the Virtex-5 FPGA SSO calculator must be used to ensure that I/O utilization does not exceed the limit. Information on the calculator is available under the “Full Device...

  • Page 306: Nominal Pcb Specifications

    Note: In cases where PCB parameters do not meet all requirements listed below, the Virtex-5 FPGA SSO Calculator must be used to determine the SSO limit, according to the physical factors of the unique PCB.

  • Page 307: Nominal Sso Limit

    Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank Voltage IOSTANDARD Limit per 20-pin Bank Limit per 40-pin Bank 1.2V HSTL_I_12 LVCMOS12_2_slow LVCMOS12_4_slow LVCMOS12_6_slow LVCMOS12_8_slow LVCMOS12_2_fast LVCMOS12_4_fast LVCMOS12_6_fast LVCMOS12_8_fast Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 308 LVCMOS15_2_slow LVCMOS15_4_slow LVCMOS15_6_slow LVCMOS15_8_slow LVCMOS15_12_slow LVCMOS15_16_slow LVCMOS15_2_fast LVCMOS15_4_fast LVCMOS15_6_fast LVCMOS15_8_fast LVCMOS15_12_fast LVCMOS15_16_fast LVDCI_15 50 Ω HSTL_I_15 HSTL_I_15_DCI HSTL_II_15 HSTL_II_15_DCI HSTL_III_15 HSTL_III_15_DCI HSTL_IV_15 HSTL_IV_15_DCI HSLVDCI_15 50 Ω DIFF_HSTL_I_15 DIFF_HSTL_I_15_DCI DIFF_HSTL_II_15 DIFF_HSTL_II_15_DCI www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 309 LVCMOS18_6_fast LVCMOS18_8_fast LVCMOS18_12_fast LVCMOS18_16_fast LVDCI_18 50 Ω HSTL_I_18 HSTL_I_DCI_18 HSTL_II_18 HSTL_II_DCI_18 HSTL_III_18 HSTL_III_DCI_18 HSTL_IV_18 HSTL_IV_DCI_18 SSTL18_I SSTL18_I_DCI SSTL18_II SSTL18_II_DCI HSLVDCI_18 50 Ω DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 310 LVCMOS25_12_slow LVCMOS25_16_slow LVCMOS25_24_slow LVCMOS25_2_fast LVCMOS25_4_fast LVCMOS25_6_fast LVCMOS25_8_fast LVCMOS25_12_fast LVCMOS25_16_fast LVCMOS25_24_fast LVDCI_25 50 Ω SSTL2_I SSTL2_I_DCI SSTL2_II SSTL2_II_DCI HSLVDCI_25 50 Ω DIFF_SSTL_I DIFF_SSTL_I_DCI DIFF_SSTL_II DIFF_SSTL_II_DCI LVPECL_25 BLVDS_25 LVDS_25 LVDSEXT_25 RSDS_25 HT_25 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 311 LVCMOS33_4_slow LVCMOS33_6_slow LVCMOS33_8_slow LVCMOS33_12_slow LVCMOS33_16_slow LVCMOS33_24_slow LVCMOS33_2_fast LVCMOS33_4_fast LVCMOS33_6_fast LVCMOS33_8_fast LVCMOS33_12_fast LVCMOS33_16_fast LVCMOS33_24_fast LVTTL_2_slow LVTTL_4_slow LVTTL_6_slow LVTTL_8_slow LVTTL_12_slow LVTTL_16_slow LVTTL_24_slow LVTTL_2_fast LVTTL_4_fast LVTTL_6_fast LVTTL_8_fast LVTTL_12_fast LVTTL_16_fast LVTTL_24_fast PCI33_3 PCI66_3 PCIX Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 312: Actual Sso Limits Versus Nominal Sso Limits

    LVDCI_33 50 Ω HSLVDCI_33 50 Ω Actual SSO Limits versus Nominal SSO Limits The Virtex-5 FPGA SSO limits are defined for a set of nominal system conditions in Table 6-40. To compute the actual limits for a specific user's system, the “Parasitic Factors...
  • Page 313 ) × 9 mV/pF) + V /((C – C DISTURBANCE_NOM LOAD_USER LOAD_NOM DISTURBANCE_NOM = 600 mV/((22 pF – 15 pF) × 9 mV/pF) + 600 mV = 600 mV/663 mV = 0.905 Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 314: Weighted Average Calculation Of Sso

    SSO Contribution (3) 19/40 Finally, the bank SSO is calculated: Bank 1 SSO = SSO contribution (1) + SSO contribution (2) + SSO Contribution (3) = 30% + 20% + 48% www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 315: Full Device Sso Calculator

    (versus the peripheral I/O architecture of previous devices), there is a separate tab at the bottom of the SSO calculator display for each Virtex-5 FPGA package. This customizing allows for the arrangement of physically adjacent banks (as...
  • Page 316 Chapter 6: SelectIO Resources www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 317: Chapter 7: Selectio Logic Resources

    In addition, Virtex-5 FPGAs implement the following architectural features that are also supported in Virtex-4 FPGAs: • IODELAY provides users control of an adjustable, fine-resolution delay element • SAME_EDGE output DDR mode • SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 318: Ilogic Resources

    The reset condition predominates over the set condition. Table 7-1 Table 7-2 describe the operation of SR in conjunction with REV. Table 7-1: Truth Table when SRVAL = 0 (Default Condition) Function Reset Reset www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 319: Combinatorial Input Path

    ILOGIC block. The following sections discuss the various resources within the ILOGIC blocks. All connections between the ILOGIC resources are managed in Xilinx software. Combinatorial Input Path The combinatorial input path is used to create a direct connection from the input driver to the FPGA fabric.

  • Page 320: Same_Edge_Pipelined Mode

    Figure 7-4 shows the timing diagram of the input DDR using the SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the FPGA fabric at the same time. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 321: Input Ddr Primitive (Iddr)

    DDR flip-flop. Data input (DDR) IDDR register input from IOB. Reset Synchronous/Asynchronous reset pin. Reset is asserted High. Synchronous/Asynchronous set pin. Set is asserted High. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 322: Iddr Vhdl And Verilog Templates

    Clock Event 1, the input signal becomes valid-High at the D IDOCK input of the input register and is reflected on the Q1 output of the input register at time T after Clock Event 1. ICKQ www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 323: Ilogic Timing Characteristics, Ddr

    Clock Event 9, and Q2 ICKQ at time T after Clock Event 10. ICKQ Table 7-5 describes the function and control signals of the ILOGIC switching characteristics in the Virtex-5 FPGA Data Sheet. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 324 CE1 pin to Q1 using flip-flop as a latch, propagation delay ICE1Q SR/REV pin to OQ/TQ out Note: The DDLY timing diagrams and parameters are identical to the D timing diagrams and parameters. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 325: Input/Output Delay Element (Iodelay)

    IODELAY allows incoming signals to be delayed on an individual basis. The tap delay resolution is varied by selecting an IDELAYCTRL reference clock from the range specified in the Virtex-5 FPGA Data Sheet. The IODELAY resource can function as IDELAY, ODELAY, or bidirectional delay.

  • Page 326: Iodelay Primitive

    Delayed data from one of three data input ports (IDATAIN, DATAOUT Output ODATAIN, DATAIN) IDATAIN Input Data input for IODELAY from the IOB. ODATAIN Input Data input for IODELAY from the OSERDES/OLOGIC www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 327: Iodelay Ports

    C can be locally inverted, and must be supplied by a global or regional clock buffer. This clock should be connected to the same clock in the SelectIO logic resources (when using ISERDES and OSERDES, C is connected to CLKDIV). Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 328 Table 7-9. Table 7-9: Increment/Decrement Operations Operation Reset to IDELAY_VALUE Increment tap count Decrement tap count No change Notes: 1. RST takes precedence over CE and INC. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 329: Iodelay Attributes

    HIGH_PERFORMANCE_MODE Boolean: FALSE, TRUE When TRUE, this attribute reduces the output TRUE jitter. The difference in power consumption is quantified in the Xilinx Power Estimator tool. SIGNAL_PATTERN String: DATA, DATA The SIGNAL_PATTERN attribute causes the CLOCK timing analyzer to account for the appropriate amount of delay-chain jitter in the data or clock path.

  • Page 330: Iodelay Timing

    Figure 7-9 shows an IDELAY timing diagram. It is assumed that IDELAY_VALUE = 0. X-Ref Target - Figure 7-9 DATAOUT Tap 0 Tap 1 UG190_7_09_100107 Figure 7-9: IDELAY Timing Diagram www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 331: Stability After An Increment/Decrement Operation

    Variable Delay Mode The Libraries Guide shows how to instantiate the IODELAY module in variable delay mode. IDELAYCTRL must also be instantiated when operating in this mode. See “IDELAYCTRL Overview,” page 337. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 332: Iodelay Turnaround Time Usage Model

    When using IODELAY in bidirectional mode, the turnaround time needs to be considered. Figure 7-10 shows a simplified block diagram of the IODELAY in the Virtex-5 FPGA IOB that applies to one use of the bidirectional IODELAY functionality. X-Ref Target - Figure 7-10...
  • Page 333 .C(clk), .CE(1'b1), .D1(D1), .D2(D2), .R(1'b0), .S(1'b0), .Q(ODATAIN) ODDR #( .DDR_CLK_EDGE ("SAME_EDGE"), .INIT (1'b0), .SRTYPE ("SYNC") )TRI_ODDR_INST ( .C(clk), .CE(1'b1), .D1(T1), .D2(T2), .R(1'b0), .S(1'b0), .Q(TSCONTROL) IDELAYCTRL IDELAYCTRL_INST ( .REFCLK(refclk), .RST(RST), .RDY() Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 334 ODDR ODATAIN DATAOUT OBUF IODELAY ODATAIN IDDR Delay IDATAIN Chain IBUF MUX E ODELAY_VALUE IDELAY_VALUE MUX F IODELAY_02_082107 Figure 7-11: IODELAY and IOB in Input Mode when 3-state is Disabled www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 335 I/O is an output switching to an input using 3-state control. The switching characteristics shown in the diagram are specified in the Virtex-5 FPGA Data Sheet. X-Ref Target - Figure 7-12...
  • Page 336 ODDR ODATAIN DATAOUT OBUF IODELAY ODATAIN IDDR Delay IDATAIN Chain IBUF MUX E ODELAY_VALUE IDELAY_VALUE MUX F IODELAY_04_082107 Figure 7-13: IODELAY and IOB in Output Mode when 3-state is Enabled www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 337: Idelayctrl Overview

    I/O switches from input to an output using 3-state control. The switching characteristics shown in the diagram are specified in the Virtex-5 FPGA Data Sheet. X-Ref Target - Figure 7-14...

  • Page 338: Idelayctrl Primitive

    If RDY is deasserted Low, the IDELAYCTRL module must be reset. The implementation tools allow RDY to be unconnected/ignored. Figure 7-16 illustrates the timing relationship between RDY and RST. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 339: Idelayctrl Timing

    IDELAYCTRL_REF_PRECISION REFCLK precision Reset/Startup to Ready for IDELAYCTRL IDELAYCTRLCO_RDY As shown in Figure 7-16, the Virtex-5 FPGA RST is an edge-triggered signal. X-Ref Target - Figure 7-16 REFCLK IDELAYCTRLCO_RDY ug190_7_11_041206 Figure 7-16: Timing Relationship Between RST and RDY IDELAYCTRL Locations IDELAYCTRL modules exist in every I/O column in every clock region.

  • Page 340: Idelayctrl Usage And Design Guidelines

    The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive without LOC constraints leaving the RDY output port unconnected are provided in the Libraries Guide. The resulting circuitry after instantiating the IDELAYCTRL components is illustrated Figure 7-18. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 341 Instantiated by user REFCLK REFCLK IDELAYCTRL REFCLK IDELAYCTRL Replicated for all IDELAYCTRL sites REFCLK IDELAYCTRL Auto-generated by mapper tool ug190_7_14_041306 Figure 7-19: Instantiate IDELAYCTRL Without LOC Constraints - RDY Connected Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 342 ISERDES and IDELAY components using the delay element. (IDELAY_TYPE attribute set to FIXED or VARIABLE). Once completed, IDELAYCTRL sites can be chosen and LOC constraints assigned. Xilinx strongly recommends using IDELAYCTRL with a LOC constraint. When not using an IDELAY (with IDELAY_TYPE in FIXED or VARIABLE mode) do not assign a LOC constraint to the IDELAYCTRL for that clock region.
  • Page 343 IDELAYCTRL instance with the RDY signal connected. This discussion is also valid when the RDY signal is ignored. The circuitry that results from instantiating the IDELAYCTRL components is illustrated in Figure 7-21. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 344: Ologic Resources

    OCE and TCE. Both have asynchronous and synchronous set and reset (SR and REV signals) controlled by an independent SRVAL attribute as described in Table 7-1 Table 7-2. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 345: Combinatorial Output Data And 3-State Control Path

    Figure 7-22: OLOGIC Block Diagram This section of the documentation discusses the various features available using the OLOGIC resources. All connections between the OLOGIC resources are managed in Xilinx software. Combinatorial Output Data and 3-State Control Path The combinatorial output paths create a direct connection from the FPGA fabric to the output driver or output driver control.
  • Page 346 DDR using the SAME_EDGE mode. X-Ref Target - Figure 7-24 D1A D2A D1B D2B D1C D2C D1D ug190_7_19_041206 Figure 7-24: Output DDR Timing in SAME_EDGE Mode www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 347: Clock Forwarding

    This is accomplished by tying the D1 input of the ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to forward clocks from the FPGA fabric to the output pins.

  • Page 348: Oddr Vhdl And Verilog Templates

    OLOGIC Timing Models This section discusses all timing models associated with the OLOGIC block. Table 7-15 describes the function and control signals of the OLOGIC switching characteristics in the Virtex-5 FPGA Data Sheet. Table 7-15: OLOGIC Switching Characteristics Symbol Description...
  • Page 349 D2 input of ODDR register and is reflected on the OQ output at time after Clock Event 2 (no change at the OQ output in this case). OCKQ Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 350 IOB DDR 3-state register timing. This example is shown using DDR in opposite edge mode. For other modes add the appropriate latencies as shown in Figure 7-4, page 321. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 351 Clock Event 9 (no change at the TQ output in this case) and resetting 3-state Register, reflected at the TQ output at time T after Clock Event 10 (no change at the TQ output in this case). Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 352 Chapter 7: SelectIO Logic Resources www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 353: Introduction

    ISERDES contains dedicated circuitry (including the OCLK input pin) to handle the strobe-to-FPGA clock domain crossover entirely within the ISERDES block. This allows for higher performance and a simplified implementation. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 354: Iserdes Primitive (Iserdes_Nodelay)

    The ISERDES primitive in Virtex-5 devices (shown in Figure 8-2) is ISERDES_NODELAY. X-Ref Target - Figure 8-2 BITSLIP CLKB ISERDES_NODELAY CLKDIV Primitive SHIFTOUT1 OCLK SHIFTOUT2 SHIFTIN1 SHIFTIN2 ug190_8_02_112607 Figure 8-2: ISERDES_NODELAY Primitive www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 355: Iserdes_Nodelay Ports

    ISERDES_NODELAY block. When width expansion is used, D1 of the master OSERDES is the least significant input, while Q4 of the slave ISERDES_NODELAY block is the least significant output. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 356: Bitslip Operation - Bitslip

    ISERDES_NODELAY for the other ½. The internal clock enable signal ICE shown in Figure 8-4 is derived from the CE1 and CE2 inputs. ICE drives the clock enable inputs of www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 357: High-Speed Clock Input - Clk

    Serial Input Data from IOB - D The serial input data port (D) is the serial (high-speed) data input port of the ISERDES_NODELAY. This port works in conjunction with all the Virtex-5 FPGA I/O resources to accommodate the desired I/O standards.

  • Page 358: Iserdes_Nodelay Attributes

    ISERDES_NODELAY attributes. A detailed description of each attribute follows the table. For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to the Xilinx ISE Software Manual. Table 8-2: ISERDES_NODELAY Attributes Default...

  • Page 359: Data_Width Attribute

    When set to MEMORY, the Bitslip submodule is not available (BITSLIP_ENABLE must be set to FALSE), and the OCLK port can be used. Figure 8-5 illustrates the ISERDES_NODELAY internal connections when in Memory mode. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 360: Num_Ce Attribute

    CLK driven by BUFIO, CLKDIV driven by BUFR • CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM • CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 361: Memory Interface Type

    For a differential input, the master ISERDES must be on the positive side of the differential input pair. When the input is not differential, the input buffer associated with the slave ISERDES is not available and can not be used. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 362: Guidelines For Expanding The Serial-To-Parallel Converter Bit Width

    The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the MASTER. The SLAVE only uses the ports Q3 to Q6 as an input. DATA_WIDTH applies to both MASTER and SLAVE in Figure 8-7. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 363: Iserdes Latencies

    (compared to memory mode) is due to the Bitslip submodule. ISERDES Timing Model and Parameters Table 8-4 describes the function and control signals of the ISERDES switching characteristics in the Virtex-5 FPGA Data Sheet. Table 8-4: ISERDES Switching Characteristics Symbol Description Setup/Hold for Control Lines...

  • Page 364: Timing Characteristics

    ISERDES receives the reset pulse in a different CLK cycle. The internal resets for both CLK and CLKDIV are reset asynchronously when the RST input is asserted. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 365: Iserdes Vhdl And Verilog Instantiation Template

    In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 366: Bitslip Submodule

    Pattern (8:1) Operations Pattern (8:1) Executed Executed Initial 10010011 Initial 00100111 00100111 10010011 01001110 10011100 10011100 01001110 00111001 01110010 01110010 00111001 11100100 11001001 11001001 11100100 ug190_8_10_100307 Figure 8-10: Bitslip Operation Examples www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 367 SDR and DDR mode, the total latency from when the ISERDES captures the asserted Bitslip input to when the “bit-slipped” ISERDES outputs Q1–Q6 are sampled into the FPGA logic by CLKDIV is two CLKDIV cycles. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 368: Bitslip Timing Model And Parameters

    On this same edge of CLKDIV, the first word sampled is presented to Q1–Q4 without any realignment. The actual bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in A of Figure 8-13. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 369 The third word sampled is presented to Q1–Q4 with three bits shifted to the left. The actual bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in C of Figure 8-13. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 370: Output Parallel-To-Serial Logic Resources (Oserdes)

    Prior to use, a reset must be applied to the OSERDES. The OSERDES contains an internal counter that controls dataflow. Failure to synchronize the reset with the CLKDIV will produce an unexpected output. Table 8-5 describes the relationship between CLK and CLKDIV in all modes. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 371: 3-State Parallel-To-Serial Conversion

    OSERDES Primitive The OSERDES primitive is shown in Figure 8-15. X-Ref Target - Figure 8-15 CLKDIV OSERDES Primitive SHIFTIN1 SHIFTOUT1 SHIFTIN2 SHIFTOUT2 ug190_8_15_100307 Figure 8-15: OSERDES Primitive Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 372: Oserdes Ports

    Divided Clock Input - CLKDIV This divided high-speed clock input drives the parallel side of the parallel-to-serial converters. This clock is the divided version of the clock connected to the CLK port. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 373: Parallel Data Inputs - D1 To D6

    OSERDES blocks that receive the same reset pulse come out of reset synchronized with one another. The reset timing of multiple OSERDES ports is shown in Figure 8-20, page 381. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 374: Oserdes Attributes

    The DATA_RATE_TQ attribute defines whether 3-state control is to be processed as single data rate (SDR) or double data rate (DDR). The allowed values for this attribute are SDR and DDR. The default value is DDR. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 375: Data_Width Attribute

    (e.g., DIFF_HSTL and DIFF_SSTL) cannot be used. This is because both OLOGIC blocks in an I/O tile are used by the complementary single-ended standards to transmit both legs of the signal, leaving no OLOGIC blocks available for width expansion. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 376: Guidelines For Expanding The Parallel-To-Serial Converter Bit Width

    The slave inputs used for data widths requiring width expansion are listed in Table 8-9. Table 8-9: Slave Inputs Used for Data Width Expansion Data Width Slave Inputs Used D3–D4 D3–D6 www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 377: Oserdes Latencies

    OSERDES Timing Model and Parameters This section discusses all timing models associated with the OSERDES primitive. Table 8-11 describes the function and control signals of the OSERDES switching characteristics in the Virtex-5 FPGA Data Sheet. Table 8-11: OSERDES Switching Characteristics Symbol Description...

  • Page 378: Timing Characteristics Of 2:1 Sdr Serialization

    The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDES. This latency is consistent with the Table 8-10 listing of a 2:1 SDR mode OSERDES latency of one CLK cycle. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 379: Timing Characteristics Of 8:1 Ddr Serialization

    The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the OSERDES. This latency is consistent with the Table 8-10 listing of a 8:1 DDR mode OSERDES latency of four CLK cycles. Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 380: Timing Characteristics Of 4:1 Ddr 3-State Controller Serialization

    Event 1 Event 2 CLKDIV A B C D E F G H I J K L OBUFT.O UG190_8_19_100307 Figure 8-19: OSERDES Data Flow and Latency in 4:1 DDR Mode www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 381: Reset Output Timing

    CLKDIV OSERDES0 Signal at SR Input OSERDES1 OSERDES0 Internal Reset (CLKDIV) OSERDES1 OSERDES0 Internal Reset (CLK) OSERDES1 UG070_c8_20_100307 Figure 8-20: Two OSERDES Coming Out of Reset Synchronously with One Another Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

  • Page 382: Oserdes Vhdl And Verilog Instantiation Templates

    The release of the reset signal at the SR input is retimed internally to CLK. OSERDES VHDL and Verilog Instantiation Templates The Libraries Guide includes instantiation templates of the OSERDES module in VHDL and Verilog. www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...

  • Page 383: Index

    RAM ports HSTL number of flip-flops timing models defined number of LUTs by device class I number of shift registers IDDR class I (1.8V) register/latch configuration delay element class II Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...
  • Page 384 READ_FIRST mode increment/decrement LVDS REFCLK primitive defined regional clock buffers switching characteristics LVDS_25_DCI regional clocks timing LVPECL clock buffers IDELAYCTRL defined clock nets instantiating LVTTL RDY port defined RSDS location www.xilinx.com Virtex-5 FPGA User Guide UG190 (v5.0) June 19, 2009...
  • Page 385 SRLOW SSTL Differential SSTL Class II (1.8V) Differential SSTL2 Class II (2.5V) SSTL18 Class I (1.8V) SSTL18 Class II (1.8V) SSTL2 Class I (2.5V) SSTL2 Class II (2.5V) WRITE_FIRST mode Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009...

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