Slice Srl Timing Model And Parameters (Available In Slicem Only) - Xilinx Virtex-5 FPGA User Manual

Slice SRL Timing Model and Parameters (Available in SLICEM only)

Figure 5-29
elements of the slice have been omitted for clarity. Only the elements relevant to the timing
paths described in this section are shown.
X-Ref Target - Figure 5-29
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
illustrates shift register implementation in a Virtex-5 FPGA slice. Some
DX
D address
6
CLK
W
CX
C address
6
BX
B address
6
AX
A address
6
Figure 5-29: Simplified Virtex-5 FPGA Slice SRL
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CLB / Slice Timing Models
SRL
DI1
O6
A MC31
CLK WE
SRL
DI1
O6
A MC31
CLK WE
SRL
DI1
O6
A MC31
CLK WE
SRL
DI1
O6
A MC31
CLK WE
UG190_5_29_050506
D
C
B
A
DMUX
207