Block Ram Port Signals; Clock - Clk[A|B]; Enable - En[A|B]; Byte-Wide Write Enable - We[A|B] - Xilinx Virtex-5 FPGA User Manual

Block RAM Port Signals

Each block RAM port operates independently of the other while accessing the same set of
36K-bit memory cells.

Clock - CLK[A|B]

Each port is fully synchronous with independent clock pins. All port input pins have setup
time referenced to the port CLK pin. The output data bus has a clock-to-out time
referenced to the CLK pin. Clock polarity is configurable (rising edge by default).

Enable - EN[A|B]

The enable pin affects the read, write, and set/reset functionality of the port. Ports with an
inactive enable pin keep the output pins in the previous state and do not write data to the
memory cells. Enable polarity is configurable (active High by default).

Byte-wide Write Enable - WE[A|B]

To write the content of the data input bus into the addressed memory location, both EN
and WE must be active within a set-up time before the active clock edge. The output
latches are loaded or not loaded according to the write configuration (WRITE_FIRST,
READ_FIRST, NO_CHANGE). When inactive, a read operation occurs, and the contents of
the memory cells referenced by the address bus appear on the data-out bus, regardless of
the write mode attribute. Write enable polarity is not configurable (active High).

Register Enable - REGCE[A|B]

The register enable pin (REGCE) controls the optional output register. When the RAM is in
register mode, REGCE = 1 registers the output into a register at a clock edge. The polarity
of REGCE is not configurable (active High).

Set/Reset - SSR[A|B]

In latch mode, the SSR pin forces the data output latches, to contain the value SRVAL. See
"Block RAM Attributes," page
data output registers can also be forced by the SSR pin to contain the value SRVAL. SSR
does not affect the latched value. The data output latches or output registers are
synchronously asserted to 0 or 1, including the parity bit. Each port has an independent
SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM memory cells and
does not disturb write operations on the other port. Similar to the read and write
operation, the set/reset function is active only when the enable pin of the port is active.
Set/reset polarity is configurable (active High by default).
Address Bus - ADDR[A|B]<13:#><14:#><15:#>
The address bus selects the memory cells for read or write. The data bit width of the port
determines the required address bus width for a single RAMB18 or RAMB36, as shown in
Table 4-6
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
128. When the optional output registers are enabled, the
and Table 4-7.
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Block RAM Port Signals
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