Global Clock Buffer Primitives - Xilinx Virtex-5 FPGA User Manual

Chapter 1: Clock Resources

Global Clock Buffer Primitives

The primitives in
Table 1-2: Global Clock Buffer Primitives
Notes:
1. All primitives are derived from a software preset of BUFGCTRL.
2. This primitive replaces the BUFGMUX_VIRTEX4 primitive.
BUFGCTRL
The BUFGCTRL primitive shown in
clocks. All other global clock buffer primitives are derived from certain configurations of
BUFGCTRL. The ISE® software tools manage the configuration of all these primitives.
BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control
lines, IGNORE0 and IGNORE1. These six control lines are used to control the input I0 and
I1.
X-Ref Target - Figure 1-1
28
Table 1-2
(1)
Primitive
BUFGCTRL
BUFG
BUFGCE
BUFGCE_1
BUFGMUX
BUFGMUX_1
(2)
BUFGMUX_CTRL
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are different configurations of the global clock buffers.
Input Output
I0, I1 O CE0, CE1, IGNORE0, IGNORE1, S0, S1
I O –
I O CE
I O CE
I0, I1 O S
I0, I1 O S
I0, I1 O S
Figure 1-1, can switch between two asynchronous
BUFGCTRL
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
ug190_1_01_032206
Figure 1-1: BUFGCTRL Primitive
Control
O
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009