Case 3: Reading From A Full Fifo - Xilinx Virtex-5 FPGA User Manual

Chapter 4: Block RAM

Case 3: Reading From a Full FIFO

Prior to the operations performed in
X-Ref Target - Figure 4-23
Clock Event 1 and Clock Event 2: Read Operation and Deassertion of Full Signal
During a read operation on a full FIFO, the content of the FIFO at the first address is
asserted at the DO output pins of the FIFO. Two RDEN operations ensure that the FIFO is
no longer full, and after three WRCLK cycles the FULL pin is deasserted.
The example in
are with respect to read-clock. Clock event 4 appears three write-clock cycles after clock
event 2.
•
•
•
If the rising RDCLK edge is close to the rising WRCLK edge, FULL could be deasserted one
WRCLK period later.
Clock Event 3 and Clock Event 5: Read Operation and Deassertion of Almost
FULL Signal
Three write-clock cycles after the fourth data is read from the FIFO, the Almost FULL pin
is deasserted to signify that the FIFO is not in the almost FULL state.
The example in
respect to read-clock, while clock event 5 is with respect to write-clock. Clock event 5
appears three write-clock cycles after clock event 3.
•
•
154
1 2
WRCLK
WREN
RDCLK
T
FCCK_RDEN
RDEN
T
FCKO_DO
00
DO
FULL
AFULL
Figure 4-23: Reading From a Full FIFO
Figure 4-23
At time T , before clock event 1 (RDCLK), read enable becomes valid at the
FCCK_RDEN
RDEN input of the FIFO.
At time T , after clock event 1 (RDCLK), data 00 becomes valid at the DO
FCKO_DO
outputs of the FIFO.
At time T , after clock event 4 (WRCLK), FULL is deasserted.
FCKO_FULL
Figure 4-23
Read enable remains asserted at the RDEN input of the FIFO.
At time T , after clock event 5 (RDCLK), Almost FULL is deasserted at the
FCKO_AFULL
AFULL pin.
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Figure 4-23, the FIFO is completely full.
3 4
01 02 03
reflects both standard and FWFT modes. Clock event 1 and 2
reflects both standard and FWFT modes. Clock event 3 is with
5
04 05 06
T
FCKO_AFULL
T
FCKO_FULL
ug190_4_19_040606
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009