Input Termination To Vcco/2 (Split Termination) - Xilinx Virtex-5 FPGA User Manual

Chapter 6: SelectIO Resources
Figure 6-9
X-Ref Target - Figure 6-9
Input Termination to V
Some I/O standards (e.g., HSTL Class I and II) require an input termination voltage of
V
X-Ref Target - Figure 6-10
This is equivalent to having a split termination composed of two resistors. One terminates
to V
V
resistors, i.e., the resistors to V
Both HSTL and SSTL standards need 50 Ω external reference resistors. The DCI input
standards supporting split termination are shown in
Table 6-1: DCI Input Standards Supporting Split Termination
226
illustrates DCI single termination inside a Virtex-5 device.
Figure 6-9: Input Termination Using DCI Single Termination
CCO
/2 (see Figure 6-10).
CCO
Figure 6-10: Input Termination to V
, the other to ground. The resistor values are 2R. DCI provides termination to
CCO
/2 using split termination. The termination resistance is set by the external reference
CCO
HSTL_I_DCI DIFF_HSTL_I_DCI
HSTL_I_DCI_18 DIFF_HSTL_I_DCI_18
HSTL_II_DCI DIFF_HSTL_II_DCI
HSTL_II_DCI_18 DIFF_HSTL_II_DCI_18 SSTL18_II_DCI
HSTL_II_T_DCI
HSTL_II_T_DCI_18
www.xilinx.com
IOB
V
CCO
R
Z
0
V
REF
Virtex-5 DCI
UG190_6_07_021206
/2 (Split Termination)
V /2
CCO
IOB
R
Z
0
V
REF
Virtex-5 FPGA
and ground are each twice the reference resistor value.
CCO
SSTL2_I_DCI
SSTL2_II_DCI
SSTL18_I_DCI
SSTL2_II_T_DCI
SSTL18_II_T_DCI
UG190_c6_08_022609
/2 without DCI
CCO
Table 6-1.
DIFF_SSTL2_I_DCI
DIFF_SSTL2_II_DCI
DIFF_SSTL18_I_DCI
DIFF_SSTL18_II_DCI
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009