Hstl Class Iii (1.8V) - Xilinx Virtex-5 FPGA User Manual

Chapter 6: SelectIO Resources

HSTL Class III (1.8V)

Figure 6-62
Class III (1.8V).
X-Ref Target - Figure 6-62
Table 6-25
Table 6-25: HSTL Class III (1.8V) DC Voltage Specifications
Notes:
1. V
2. Per EIA/JESD8-6, "The value of V
270
shows a sample circuit illustrating a valid termination technique for HSTL
External Termination
IOB
HSTL_III_18
DCI
IOB
HSTL_III_DCI_18
Figure 6-62: HSTL Class III (1.8V) Termination
lists the HSTL Class III (1.8V) DC voltage specifications.
V
CCO
(2)
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
(1)
I at V (mA)
OH OH
(1)
I at V (mA)
OL OL
and V for lower drive currents are sample tested.
OL OH
the use conditions specified by the user."
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V = 1.8V
TT
IOB
R P = Z 0 = 50Ω
Z 0
V
IOB
V = 1.8V
CCO
R = Z 0 = 50Ω
VRP
Z 0
V
Min
1.7
–
–
V + 0.1
REF
–
V – 0.4
CCO
–
–8
24
is to be selected by the user to provide optimum noise margin in
REF
HSTL_III_18
+
–
= 1.1V
REF
HSTL_III_DCI_18
+
–
= 1.1V
REF
ug190_6_59_030306
Typ Max
1.8 1.9
1.1 –
V –
CCO
– –
– V – 0.1
REF
– –
– 0.4
– –
– –
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009