Peripheral Device Ks0713 - Xilinx Virtex-5 FPGA ML561 User Manual

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Peripheral Device KS0713

Figure C-2
VDD
VSS
Circuit
Circuit
Circuit
KS0713 Samsung
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
is a block diagram of the Samsung KS0713.
33 Common
Driver
Circuits
V/F
Page I/O
Address Buffer
Circuit
V/R
V/C
Figure C-2: KS0713 Block Diagram
www.xilinx.com
132 Segment
Driver
Circuits
Segment Controller
Display Data RAM Line
65 x132 = Address
8580 Bits Circuit
Column Address
Circuit
Status Register Instruction Register
Bus Holder Instruction Decoder
MPU Interface (Parallel & Serial)
Hardware Schematic Diagram
33 Common
Driver
Circuits
Common Controller
Display
Timing
Generator
Circuit
Oscillator
UG199_C_02_050106
121