Timing Characteristics Of 4:1 Ddr 3-State Controller Serialization - Xilinx Virtex-5 FPGA User Manual

Chapter 8: Advanced SelectIO Logic Resources
The second word IJKLMNOP is sampled into the master and slave OSERDES from the D1–
D6 and D3–D4 inputs, respectively.
Clock Event 4
Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ,
a total of eight bits transmitted in one CLKDIV cycle.
The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the
OSERDES. This latency is consistent with the
OSERDES latency of four CLK cycles.

Timing Characteristics of 4:1 DDR 3-State Controller Serialization

The operation of a 3-State Controller is illustrated in
case shown in a bidirectional system where the IOB must be frequently 3-stated.
X-Ref Target - Figure 8-19
380
D1 A
D2
B
D3
C
D4
D
CLKDIV
CLK
T1
1
T2 1
1
T3
T4 1
OQ
TQ
OBUFT.O
Figure 8-19: OSERDES Data Flow and Latency in 4:1 DDR Mode
www.xilinx.com
Table 8-10 listing of a 8:1 DDR mode
Figure 8-19. The example is a 4:1 DDR
Clock Clock
Event 1 Event 2
E I
F J
G K
H L
0
0
1
0
A B C D E F G H I J K L
E F H
1
1
1
1
UG190_8_19_100307
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009