Power Monitor Circuitry - Xilinx Virtex-5 FPGA ML550 User Manual

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Power Monitor Circuitry

ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
Downloaded from Elcodis.com electronic components distributor
The ML550 hosts a 2 x 13 0.1-inch male header connector which provides test points for the
ML550 power regulators as shown in
Table 3-16: Power Monitor Connector P72 Pinout
Pin # Signal Name
1 VCC1V0_VINT_S+
2 VCC1V0_VINT_S–
3 VCC1V0_VINT_MON
4 Dgnd
5 VCC2V5_VAUX_S+
6 VCC2V5_VAUX_S–
7 VCC2V5_VAUX_MON
8 Dgnd
9 VCC2V5_VCCO_S+
10 VCC2V5_VCCO_S–
11 VCC2V5_VCCO_MON
12 Dgnd
13 VCC2V5_S+
14 VCC2V5_S–
15 VCC2V5_MON
16 Dgnd
17 VCC3V3_SYS_S+
18 VCC3V3_SYS_S–
19 VCC3V3_SYS_MON
20 VCC5
21 NC
22 NC
23 NC
24 VCC5_MON
25 VCC5_S+
26 VCC5_S–
The regulator outputs are connected to a series Kelvin resistor, which is then connected to
the target power plane. ML550 voltage regulator topology is discussed in detail in sections
"Voltage Regulators (TI PTH05000)," page 29
summary of the regulator connections to P72 is given in
Note:
As indicated in Note 3 beneath
www.xilinx.com
ML550 System Monitor and Power Monitor Support
Table 3-16.
R REF Schematic
KELVIN
R386 20, 23
R386 20, 23
R386 20, 23
R384 20, 24
R384 20, 24
R384 20, 24
R385 20, 22
R385 20, 22
R385 20, 22
R383 20, 22
R383 20, 22
R383 20, 22
R387 20, 24
R387 20, 24
R387 20, 24
19, 20
R201 19,20
R201 19,20
R201 19,20
and "Power Monitor Connector," page
Table 3-12, page
Table 3-12, the S+ and S– pins of P72 are reversed.
Notes
S– actual
S+ actual
20
S– actual
S+ actual
20
S– actual
S+ actual
20
S– actual
S+ actual
20
S– actual
S+ actual
20
20
20
S– actual
S+ actual
32. A
33.
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