Controller - Lcd Panel Connections - Xilinx Virtex-5 FPGA ML550 User Manual

Appendix C: LCD Interface
Table C-3: KS0713 Pin Connections
Connector J1 Connector J2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
LCD Control Pins
70
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Controller – LCD Panel Connections
The controller die, KS0713, connects to the LCD glass panel and user connection pins via a
small PCB. Other necessary pins have default connections on the PCB.
how all pins of the die are connected. The pins in
PCB, and the other pins connect to the user-accessible connectors.
PCB
Connection
16 1
15 2
14 3
13 4
12 5
11 6
10 7
9 8
8 9
7 10
6 11
5 12
4 13
3 14
15
1 16
2 17
blue
Signal
Connected to
Name
CS1B
RESETB
RS
RW_WR
E_RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
MI
PS
VSS
VDD
VDD CS2
VDD DUTY0
VDD DUTY1
VDD MS
VDD CLS
VSS TEMPS
VDD INTRS
VSS HPM
VDD BSTS
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Table C-3
connect to default values on the
Description
Chip enable is active Low
Initialize the LCD
Register select
Read/Write
Enable/Read
8-bit bidirectional data bus.
In serial mode DB0-DB5 are High
impedance, DB6 is the serial clock
input, and DB7 is the serial data
input.
Processor mode select
Parallel or Serial
Ground
Power Supply
Active High chip enable.
LCD driver duty ratio. Set to 1/65
Master / Slave operation. Set to
Master
Built-in oscillator enable
Set to -0.05%/° C
Internal resistors used
Normal mode set
Voltage converter input is VDD
(2.4<VDD<3.6)
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
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