Global Clock Inputs - Xilinx Virtex-5 FPGA ML555 User Manual

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Global Clock Inputs

Global clock inputs to the FPGA are summarized in
connected to FPGA bank 3.
Table 3-19: FPGA Global Clock Inputs
FPGA Pins Signal Name
L18 LVPECL_200M_N
K17 LVPECL_200M_P
H18 SMA_GCLKN
H17 SMA_GCLKP
H19 LVDSCLKMOD1_P
H20 LVDSCLKMOD1_N
(4)
J20 SATA_MGT_GCLKP
(4)
J21 SATA_MGT_GCLKN
G16 SFP_MGT_GCLKN
G15 SFP_MGT_GCLKP
L19 FPGA_GCLK_30MHZ
H14 P0_RCLK1
J19 P1_RCLK1
J14 PCIBUSCLK2
(2)
J16 PCIE_GCLK_P
(2)
J17 PCIE_GCLK_N
(4)
H15 SATA_MGT_CLKSEL
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
200 MHz LVPECL oscillator Y3
200 MHz LVPECL oscillator Y3
(2,5) SMA Connector J11
(2,5) SMA Connector J10
Clock Synthesizer 1
Clock Synthesizer 1
Selectable: 125 MHz Oscillator or Clock Synthesizer 2
Selectable: 125 MHz Oscillator or Clock Synthesizer 2
125 MHz LVDS Oscillator
125 MHz LVDS Oscillator
(3) 30 MHz Oscillator
(3) Port 0 Ethernet PHY Receive Clock (if the EPHY daughtercard is installed)
(3) Port 1 Ethernet PHY Receive Clock (if the EPHY daughtercard is installed)
(3) P1-B16 active only when the ML555 board is installed in a PCI bus
connector. Not active when the ML555 board is installed in a PCI Express
connector.
Global clock input available only if an ICS874003-02 PCI Express clock jitter
attenuator circuit is installed on the ML555 board at location U16 (not the
default board configuration). This clock is 100, 125, or 250 MHz as selected
by the CPLD controls. The default is a 250 MHz spread spectrum clock
generated from the add-in card PCI Express input clock on connector P13.
Global clock input available only if an ICS874003-02 PCI Express clock jitter
attenuator circuit is installed on the ML555 board at location U16 (this is not
the default board configuration). This clock is 100, 125, or 250 MHz as
selected by the CPLD controls. The default is a 250 MHz spread spectrum
clock generated from the add-in card input clock for PCI Express operation
on connector P13.
FPGA output used to select the fixed 125 MHz oscillator or the Clock
Synthesizer 2 output to be routed to GTP_DUAL tile X0Y5 MGTREFCLK
and SMA_MGT_GCLK global clock inputs. The ML555 board has a 4.7KΩ
pull-up resistor to 2.5V to provide default selection of clock synthesizer 2 as
the output of the Clock Mux block shown in
www.xilinx.com
Table 3-19. Global clocks are
Clock Source
(3)
Figure 3-8
Clock Generation
and Figure 3-9.
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