Hardware Schematic Diagram - Xilinx Virtex-5 FPGA ML550 User Manual

Appendix C: LCD Interface
Table C-1
Table C-1: Display Controller Specifications
The on-chip RAM size is 65x132 = 8580 bits.

Hardware Schematic Diagram

LCD-BUS
3.3V
DIP1_4
64
summarizes the controller specifications.
Parameter
Supply voltage
LCD driving voltage
Power consumption
Sleep mode
Standby mode
LCD_D[7:0]
IC19
ENA, R/W, RSEL, CS1B
IC22
IC23
Figure C-1: Display Schematic Diagram
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Specification
2.4V to 3.6V (V )
DD
4V to 15V (V = V0 - V
LCD DD
70μA typical (V = 3V, x4 boost, V0 = 11V,
DD
internal supply = ON)
2μA
10μA
LED
Rst MI - +
3.3V 3.3V
68xx
68xx
Default = 68xx
Default =
Resistor to Gnd
Backlight ON/OFF
ML550 Networking Interfaces Platform
)
Vcc Gnd
3.3V
UG202_C_01_050906
UG202 (v1.4) April 18, 2008
R