Xilinx Dci - Xilinx Virtex-5 FPGA User Manual

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Xilinx DCI

DCI uses two multi-purpose reference pins in each bank to control the impedance of the
driver or the parallel termination value for all of the I/Os of that bank. The N reference pin
(VRN) must be pulled up to V
must be pulled down to ground by another reference resistor. The value of each reference
resistor should be equal to the characteristic impedance of the PC board traces, or should
be twice that value. See
228.
When a DCI I/O standard is used on a particular bank, the two multi-purpose reference
pins cannot be used as regular I/Os. However, if DCI I/O standards are not used in the
bank, these pins are available as regular I/O pins. The Virtex-5 Family Packaging
Specifications gives detailed pin descriptions.
DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or
off. The impedance is adjusted to match the external reference resistors. The impedance
adjustment process has two phases. The first phase compensates for process variations by
controlling the larger transistors in the I/Os. It occurs during the device startup sequence.
The second phase maintains the impedance in response to temperature and supply voltage
changes by controlling the smaller transistors in the I/Os. It begins immediately after the
first phase and continues indefinitely, even while the device is operating. By default, the
DONE pin does not go High until the first phase of the impedance adjustment process is
complete.
The coarse impedance calibration during the first phase of impedance adjustment can be
invoked after configuration by instantiating the DCIRESET primitive. By toggling the RST
input to the DCIRESET primitive while the device is operating, the DCI state machine is
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
DCI cascading must extend across consecutive banks in the same column. It is not
possible to skip banks when using DCI cascading. For example, consider four banks
in a column A, B, C, and D, from top to bottom. In this case, the following are valid
possibilities for DCI cascading, assuming all other guidelines are met:
♦
DCI cascading can extend to Bank A, Bank C, or both banks.
♦
DCI cascading can also extend to Bank D, since Bank D is in the same column.
However, DCI cascading must also extend to the intervening Bank C. If DCI I/O
standards are implemented in Bank C, DCI I/O banking compatibility must be
observed across all three banks (B, C, and D).
DCI cascading can span the entire column as long as the above guidelines are met.
Locate adjacent banks. Bank location information is best determined from partgen
generated package files (partgen -v XC5VLX50TFF1136). The resulting package
file with a .pkg extension contains XY I/O location information. The X designator
indicates I/Os in the same column. The Y designator indicates the position of an I/O
within a specific bank. The bank number is also shown. Consecutive Y locations
across bank boundaries show adjacent banks. For example, the XC5VLXT in an
FF1136 package shows bank 11 starting with I/O X0Y159 end ending with I/O
location X0Y120. Bank 13 starts with I/O X0Y119 and ends with X0Y80. Bank 15 starts
with X0Y199 and ends with X0Y160. This indicates that bank 13 is to the south of bank
11, and bank 15 is to the north. As the Y coordinates of these two banks are
consecutive, these two banks are considered consecutive banks and can be DCI
cascaded. It is possible to cascade through an unbonded bank.
DCI cascade is enabled by using the DCI_CASCADE constraint described in the
constraints guide.
"Driver with Termination to V
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SelectIO Resources General Guidelines
by a reference resistor, and the P reference pin (VRP)
CCO
CCO
/2 (Split Termination)," page
223