Almost Empty Flag; Read Error Flag; Full Flag; Write Error Flag - Xilinx Virtex-5 FPGA User Manual

Chapter 4: Block RAM
relationship, it takes several cascaded flip-flops to guarantee that such a move does not
cause glitches or metastable problems. The falling edge of EMPTY is thus delayed by
several RDCLK periods after the first write into the previously empty FIFO. This delay
guarantees proper operation under all circumstances, and causes an insignificant loss of
performance after the FIFO had gone empty.

Almost Empty Flag

The Almost Empty flag is set when the FIFO contains the number of entries specified by
the ALMOST_EMPTY_OFFSET value or fewer entries. The Almost Empty flag warns the
user to stop reading. It deasserts when the number of entries in the FIFO is greater than the
ALMOST_EMPTY_OFFSET value plus one. Assertion and deassertion is synchronous to
RDCLK. Flag latency is described in
When a Virtex-5 FPGA FIFO is instantiated in FWFT mode, ALMOST_EMPTY_OFFSET
must be set to a value that satisfies
For example, if the read frequency is 1/2 the write frequency, ALMOST_EMPTY_OFFSET
needs to be greater than or equal to 8. This equation also means that any time the read
frequency is greater than or equal to the write frequency, any legal value of
ALMOST_EMPTY_OFFSET works.

Read Error Flag

Once the Empty flag has been asserted, any further read attempts will not increment the
read address pointer but will trigger the Read Error flag. The Read Error flag is deasserted
when Read Enable or Empty is deasserted Low. The Read Error flag is synchronous to
RDCLK.

Full Flag

The Full flag is synchronous with WRCLK, and is asserted when there are no more
available entries in the FIFO queue. When the FIFO is full, the write pointer will be frozen.
The Virtex-5 FPGA Full flag is deasserted three write clock cycles after two subsequent
read operations. In Virtex-4 FPGA designs a Full flag is asserted one write clock cycle after
the last write, and is deasserted three write clock cycle after the first read.

Write Error Flag

Once the Full flag has been asserted, any further write attempts will not increment the
write address pointer but will trigger the Write Error flag. The Write Error flag is
deasserted when Write Enable or Full is deasserted Low. This signal is synchronous to
WRCLK.

Almost Full Flag

The Almost Full flag is set when the FIFO has the number of available empty spaces
specified by the ALMOST_FULL_OFFSET value or fewer spaces. The Almost Full flag
warns the user to stop writing. It deasserts when the number of empty spaces in the FIFO
is greater than the ALMOST_FULL_OFFSET value plus one. Assertion and deassertion is
synchronous to WRCLK. Flag latency is described in
146
ALMOST_EMPTY_OFFSET
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Table 4-16.
Equation 4-1.
⎛ WRCLK frequency
≥ ×
------------------------------------------------- -
4 Roundup
⎝
RDCLK frequency
Table
⎞
Equation 4-1
⎠
4-16.
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009